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Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM)[1] of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalent standalone DRAM chips used as external memory, but the performance advantages of placing eDRAM onto the same chip as the processor outweigh the cost disadvantages in many applications.

Embedding memory on the ASIC or processor allows for much wider buses and higher operation speeds, and due to much higher density of DRAM in comparison to SRAM, larger amounts of memory can be installed on smaller chips if eDRAM is used instead of eSRAM. eDRAM requires additional fab process steps compared with embedded SRAM, which raises cost, but the 3× area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design.

eDRAM memories, like all DRAM memories, require periodic refreshing of the memory cells, which adds complexity. However, if the memory refresh controller is embedded along with the eDRAM memory, the remainder of the ASIC can treat the memory like a simple SRAM type such as in 1T-SRAM. It is also possible to use architectural techniques to mitigate the refresh overhead in eDRAM caches.[2]

eDRAM is used in various products, including IBM's POWER7 processor,[3] Intel's Haswell CPUs with GT3e integrated graphics,[4] many game consoles and other devices, such as Sony's PlayStation 2, Sony's PlayStation Portable, Nintendo's GameCube, Nintendo's Wii, Nintendo's Wii U, Apple Inc.'s iPhone, Microsoft's Zune HD, and Microsoft's Xbox 360.

Use of eDRAM in various products
Product name Amount of
Intel Haswell, Iris Pro Graphics 5200 (GT3e) 128 MB
Intel Broadwell, Iris Pro Graphics 6200 (GT3e) 128 MB
Intel Skylake, Iris Graphics 540 and 550 (GT3e) 64 MB
Intel Skylake, Iris Pro Graphics 580 (GT4e) 64 or 128 MB
Intel Coffee Lake, Iris Plus Graphics 655 (GT3e) 128 MB
PlayStation 2 4 MB
Xbox 360 10 MB
Wii U 32 MB

Certain software utilities can model eDRAM caches.[5]


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