Elbrus 2000

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Elbrus 2000
Produced 2008
Designed by Moscow Center of SPARC Technologies (MCST)
Common manufacturer(s)
Max. CPU clock rate 300 MHz
Instruction set Elbrus, x86
Cores 1

The Elbrus 2000, E2K (Russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.

It supports two instruction set architecture (ISA):

Thanks to its unique architecture Elbrus 2000 can execute 20 instructions per clock, so even with its modest clock speed it can compete with much faster clocked superscalar microprocessors when running in native VLIW mode.[1][2]

For security reasons the Elbrus 2000 architecture implements dynamic data type-checking during execution. In order to prevent unauthorized access, each pointer has additional type information that is verified when the associated data is accessed.[3]

Supported operating systems[edit]

Elbrus 2000 information[edit]

Produced 2005
Process CMOS 0.13 µm
Clock rate 300 MHz
Peak performance
  • 64 bit: 5.8 GIPS
  • 32 bit: 9.5 GIPS
  • 16 bit: 12.3 GIPS
  • 8 bit: 22.6 GIPS
Data format
  • integer: 32, 64
  • float: 32, 64, 80
Cache
  • 64 KB L1 instruction cache
  • 64 KB L1 data cache
  • 256 KB L2 cache
Data transfer rate
  • to cache: 9.6 GByte/s
  • to main memory: 4.8 GByte/s
Transistors 75.8 million
Connection layers 8
Packing / pins HFCBGA / 900
Chip size 31×31×2.5 mm
Voltage 1.05 / 3.3 V
Power consumption 6 W

Successors[edit]

References[edit]

External links[edit]