Epyc

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AMD Epyc
AMD Epyc wordmark.svg
General information
LaunchedJune 2017
Marketed byAMD
Designed byAMD
Common manufacturer(s)
Performance
Max. CPU clock rate2.7 GHz to 4.1 GHz
Architecture and classification
Technology node14 nm to 7 nm
MicroarchitectureZen
Zen 2
Zen 3
Zen 4
Zen 4c
Instruction setx86-64
MMX(+), SSE1, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, AVX2, FMA3, CVT16/F16C, ABM, BMI1, BMI2
AES, CLMUL, RDRAND, SHA, SME
AMD-V, AMD-Vi
Physical specifications
Cores
  • up to 64 cores/128 threads per socket
Socket(s)
Products, models, variants
Core name(s)
  • Naples
  • Rome
  • Milan
  • Genoa
  • Bergamo
Brand name(s)
  • Epyc
History
PredecessorOpteron

EPYC is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.[1] Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using the Infinity Fabric interconnect.

History[edit]

In March 2017, AMD announced plans to re-enter the server market with a platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May.[2] That June, AMD officially launched Epyc 7001 series processors, offering up to 32 cores per socket, and enabling performance that allowed Epyc to be competitive with the competing Intel Xeon product line.[3] Two years later, in August 2019, the Epyc 7002 'Rome' series processors, based on the Zen 2 microarchitecture, launched, doubling the core count per socket to 64, and increasing per-core performance dramatically over the last generation architecture.

In March 2021, AMD launched the Epyc 7003 'Milan' series, based on the Zen 3 microarchitecture.[4] Epyc Milan brought the same 64 cores as Epyc Rome, but with much higher per-core performance, with the EPYC 7763 beating the EPYC 7702 by up to 22% despite having the same number of cores and threads.[5] A refresh of the Epyc 7003 'Milan' series with 3D V-Cache named Milan-X launched March 21st, 2022, using the same cores as Epyc Milan, but with an additional 512MB of cache stacked onto the compute dies, bringing the total amount of cache per CPU to 768 MB.[6]

On November 8th, 2021, AMD unveiled the upcoming generations of AMD EPYC, also unveiling the new LGA-6096 SP5 socket that would support the upcoming generations of Epyc chips. Codenamed Genoa, the first Zen 4 based Epyc CPUs will be built on a TSMC 5nm process node and support up to 96 cores and 192 threads per socket, alongside 12 channels of DDR5[7] and 128 PCIe 5.0 lanes.[8] AMD also shared information regarding the sister-chip of Genoa, codenamed Bergamo. Bergamo will be based on a modified Zen 4 microarchitecture named Zen 4c, designed to allow for much higher core counts and efficiency at the cost of lower single-core performance, targeting cloud providers and workloads, compared to traditional high performance computing workloads.[9] Bergamo will be compatible with Socket SP5, and will support up to 128 cores and 256 threads per socket.[10]

AMD EPYC CPU Codenames[11]
Gen Year Name Cores
1st 2017 Naples 32 × Zen 1
2nd 2019 Rome 64 × Zen 2
3rd 2021 Milan 64 × Zen 3
2022 Milan-X 64 x Zen 3
4th 2022 Genoa 96 × Zen 4
2023 Bergamo 128 × Zen 4c

Design[edit]

A delidded second gen Epyc 7702, showing the die configuration

Epyc CPUs use a multi-chip-module design to enable higher yields for a CPU than traditional monolithic dies. First gen Epyc CPUs are composed of four 14 nm compute dies, each with up to 8 cores.[12][13] Cores are symmetrically disabled on dies to create lower binned products with fewer cores but the same I/O and memory footprint. Second and Third gen Epyc CPUs are composed of eight compute dies built on a 7 nm process node, and a large I/O die built on a 14 nm process node.[14] Third gen Milan-X CPUs use advanced through-silicon-vias to stack an additional die on top of each of the 8 compute dies, adding 64 MB of L3 cache per die.[15]

Epyc supports both single socket and dual socket operation. In a dual socket configuration, 64 PCIe lanes from each CPU are allocated to AMD's proprietary Infinity Fabric interconnect to allow for full bandwidth between both CPUs.[16] As such, a dual socket configuration has the same number of usable PCIe lanes as a single socket configuration. First generation Epyc CPUs had 128 PCIe 3.0 lanes, while second and third generation had 128 PCIe 4.0 lanes. All current Epyc CPUs are equipped with up to eight channels of DDR4 at varying speeds, though next gen Genoa CPUs are confirmed by AMD to support up to twelve channels of DDR5.[7][17]

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some features may require the use of additional controller chips to utilize.

An x-ray of a second gen Epyc 7702

Reception[edit]

Initial reception to Epyc was generally positive.[17] Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.[17] In 2021, Meta Platforms selected Epyc chips for its metaverse data centers.[18]

Features[edit]

CPU features table

Products[edit]

Server[edit]

First generation Epyc (Naples)[edit]

The following table lists the devices using the first generation design.

A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCI-E lanes from each processor for the communication between processors.

Model Release date
and price
Fab Chiplets Cores
(threads)
Core Config[i] Clock rate (GHz) Cache Socket &
configuration
PCIe
Lanes
Memory
support
TDP
Base Boost L1 L2 L3
All-core Max
EPYC 7351P[19] [20][21] June 2017[22]
US $750
14 nm 4 × CCD 16 (32) 8 × 2 2.4 2.9 64 KB inst.
32 KB data
per core
512 KB
per core
64 MB
8 MB per CCX
SP3
1P
128 DDR4-2666
8 channels
155/170 W
EPYC 7401P[19] [20][21] June 2017[22]
US $1075
24 (48) 8 × 3 2.0 2.8 3.0
EPYC 7551P[19][20][21] June 2017[22]
US $2100
32 (64) 8 × 4 2.55 180 W
EPYC 7251[19][20][21] June 2017[22]
US $475
8 (16) 8 × 1 2.1 2.9 32 MB
4 MB per CCX
SP3
2P
DDR4-2400
8 channels
120 W
EPYC 7261[23] Mid 2018
US $700+
2.5 64 MB
8 MB per CCX
DDR4-2666
8 channels
155/170 W
EPYC 7281[19][20][21] June 2017[22]
US $650
16 (32) 8 × 2 2.1 2.7 32 MB
4 MB per CCX
EPYC 7301[19][20][21] June 2017[22]
US $800+
2.2 64 MB
8 MB per CCX
EPYC 7351[19][20][21] June 2017[22]
US $1100+
2.4 2.9 2.9
EPYC 7371[24] Late 2018
US $1550+
3.1 3.6 3.8 180 W
EPYC 7401[19][20][21] June 2017[22]
US $1850
24 (48) 8 × 3 2.0 2.8 3.0 155/170 W
EPYC 7451[19][20][21] June 2017[22]
US $2400+
2.3 2.9 3.2 180 W
EPYC 7501[19][20][21] June 2017[22]
US $3400
32 (64) 8 × 4 2.0 2.6 3.0 155/170 W
EPYC 7551[19][20][21] June 2017[22]
US $3400+
2.55 180 W
EPYC 7571 Late 2018
N/A
2.2 ? 200 W?
EPYC 7601[19][20][21] June 2017[22]
US $4200
2.7 3.2 180 W
  1. ^ Core Complexes (CCX) × cores per CCX
A first generation Epyc die configuration
An Epyc CPU in an SP3 socket

Second generation Epyc (Rome)[edit]

First generation Epyc processor

In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture.[25] The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip providing 128 PCIe lanes in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket.[26] The 7 nm "Rome" is manufactured by TSMC.[14] It was released on August 7, 2019.[27]

Common features of these CPUs:

  • Codenamed "Rome"
  • Zen 2 Microarchitecture
  • 7 nm TSMC Process
  • SP3 Socket
  • The number of PCI-E lanes: 128
  • Release date: August 7, 2019 except EPYC 7H12 which was released on September 18, 2019
  • Memory support: eight-channel DDR4-3200
Model Price Fab Chiplets Cores
(threads)
Core config[i] Clock rate (GHz) Cache Socket &
configuration
TDP
Base Boost L1 L2 L3
All-core Max
EPYC 7232P US $450 7 nm 2 × CCD
1 × I/O
8 (16) 4 × 2 3.1 3.2 32 KB inst.
32 KB data
per core
512 KB
per core
32 MB
8 MB per CCX
SP3
1P
120 W
EPYC 7302P US $825 4 × CCD
1 × I/O
16 (32) 8 × 2 3 3.3 128 MB
16 MB per CCX
155 W
EPYC 7402P US $1250 24 (48) 8 × 3 2.8 3.35 180 W
EPYC 7502P US $2300 32 (64) 8 × 4 2.5 3.35
EPYC 7702P US $4425 8 × CCD
1 × I/O
64 (128) 16 × 4 2 3.35 256 MB
16 MB per CCX
200 W
EPYC 7252 US $475 2 × CCD
1 × I/O
8 (16) 4 × 2 3.1 3.2 64 MB
16 MB per CCX
SP3
2P
120 W
EPYC 7262 US $575 4 × CCD
1 × I/O
8 × 1 3.2 3.4 128 MB
16 MB per CCX
155 W
EPYC 7272 US $625 2 × CCD
1 × I/O
12 (24) 4 × 3 2.9 3.2 64 MB
16 MB per CCX
120 W
EPYC 7282 US $650 16 (32) 4 × 4 2.8 3.2
EPYC 7302 US $978 4 × CCD
1 × I/O
8 × 2 3 3.3 128 MB
16 MB per CCX
155 W
EPYC 7352 US $1350 24 (48) 8 × 3 2.3 3.2
EPYC 7402 US $1783 8 × 3 2.8 3.35 180 W
EPYC 7452 US $2025 32 (64) 8 × 4 2.35 3.35 155 W
EPYC 7502 US $2600 8 × 4 2.5 3.35 180 W
EPYC 7532 US $3350 8 × CCD
1 × I/O
16 × 2 2.4 3.3 256 MB
16 MB per CCX
200 W
EPYC 7542 US $3400 4 × CCD
1 × I/O
8 × 4 2.9 3.4 128 MB
16 MB per CCX
225 W
EPYC 7552 US $4025 6 × CCD
1 × I/O
48 (96) 12 × 4 2.2 3.3 192 MB
16 MB per CCX
200 W
EPYC 7642 US $4775 8 × CCD
1 × I/O
16 × 3 2.3 3.3 256 MB
16 MB per CCX
225 W
EPYC 7662 US $6150 64 (128) 16 × 4 2 3.3 225 W
EPYC 7702 US $6450 2 3.35 200 W
EPYC 7742 US $6950 2.25 3.4 225 W
EPYC 7H12 2.6 3.3 280 W
EPYC 7F32 US $2100 4 × CCD
1 × I/O
8 (16) 8 × 1 3.7 3.9 128 MB
16 MB per CCX
180 W
EPYC 7F52 US $3100 8 × CCD
1 × I/O
16 (32) 16 × 1 3.5 3.9 256 MB
16 MB per CCX
240 W
EPYC 7F72 US $2450 6 × CCD
1 × I/O
24 (48) 12 × 2 3.2 3.7 192 MB
16 MB per CCX
240 W
  1. ^ Core Complexes (CCX) × cores per CCX
The bottom side of an Epyc CPU mounted in a plastic carrier

Third generation Epyc (Milan)[edit]

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture.[28] Milan chips will use Socket SP3, with up to 64 cores on package, and support eight channel DDR4 SDRAM and 128 PCIe 4.0 lanes.[28] It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.[28]

Milan CPUs were launched by AMD on 15 March 2021.[29]

Milan-X CPUs were launched March 21st, 2022.[6] Milan-X CPUs use 3D V-Cache technology to increase the maximum L3 cache per socket capacity from 256 MB to 768 MB.[30][31][32]


Model Price Fab Chiplets Cores
(threads)
Core config[i] Clock rate (GHz) Cache Socket &
configuration
TDP
Base Boost L1 L2 L3
EPYC 7773X US $8800 7 nm 8 × CCD
1 × I/O
64 (128) 8 × 8 2.20 3.50 32 KB inst.
32 KB data
per core
512 KB
per core
768 MB
32 + 64 MB per CCX
SP3

2P

280 W
EPYC 7763 US $7890 2.45 3.40 256 MB
32 MB per CCX
SP3
2P
280 W
EPYC 7713 US $7060 2.00 3.675 225 W
EPYC 7713P US $5010 SP3
1P
EPYC 7663 US $6366 56 (112) 8 × 7 2.00 3.50 SP3
2P
240 W
EPYC 7643 US $4995 48 (96) 8 × 6 2.30 3.60 225 W
EPYC 7573X US $5590 32 (64) 8 × 4 2.80 3.60 768 MB
32 + 64 MB per CCX
280 W
EPYC 75F3 US $4860 2.95 4.00 256 MB
32 MB per CCX
EPYC 7543 US $3761 2.80 3.70 225 W
EPYC 7543P US $2730 256 MB
32 MB per CCX
SP3
1P
EPYC 7513 US $2840 2.60 3.65 128 MB
16 MB per CCX
SP3
2P
200 W
EPYC 7453 US $1570 4 × CCD
1 × I/O
28 (56) 4 × 7 2.75 3.45 64 MB
16 MB per CCX
225 W
EPYC 7473X US $3900 8 × CCD
1 × I/O
24 (48) 8 × 3 2.80 3.70 768 MB
32 + 64 MB per CCX
240 W
EPYC 74F3 US $2900 3.20 4.00 256 MB
32 MB per CCX
EPYC 7443 US $2010 4 × CCD
1 × I/O
4 × 6 2.85 4.00 128 MB
32 MB per CCX
200 W
EPYC 7443P US $1337 SP3
1P
EPYC 7413 US $1825 2.65 3.60 SP3
2P
180 W
EPYC 7373X US $4185 8 × CCD
1 × I/O
16 (32) 8 × 2 3.05 3.80 768 MB
32 + 64 MB per CCX
240 W
EPYC 73F3 US $3521 3.50 4.00 256 MB
32 MB per CCX
EPYC 7343 US $1565 4 × CCD
1 × I/O
4 × 4 3.20 3.90 128 MB
32 MB per CCX
190 W
EPYC 7313 US $1083 3.00 3.70 155 W
EPYC 7313P US $913 SP3
1P
EPYC 72F3 US $2468 8 × CCD
1 × I/O
8 (16) 8 × 1 3.70 4.10 256 MB
32 MB per CCX
SP3
2P
180 W
  1. ^ Core Complexes (CCX) × cores per CCX


Embedded[edit]

First generation Epyc (Snowy Owl)[edit]

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.[33]


Model Release
date
Fab Chiplets Cores
(threads)
Core Config[i] Clock rate (GHz) Cache Socket PCIe
lanes
Ethernet Memory
support
TDP Junction temperature (°C)
Base Boost L1 L2 L3
All-core Max
EPYC 3101 February 2018 14 nm 1 x CCD 4 (4) 1 × 4 2.1 2.9 2.9 64 KB inst.
32 KB data
per core
512 KB
per core
8 MB SP4r2 32 4 × 10GbE DDR4-2666
dual-channel
35 W 0-95
EPYC 3151 4 (8) 2 × 2 2.7 2.9 2.9 16 MB
8 MB per CCX
45 W
EPYC 3201 8 (8) 2 × 4 1.5 3.1 3.1 DDR4-2133
dual-channel
30 W
EPYC 3251 8 (16) 2.5 3.1 3.1 DDR4-2666
dual-channel
55 W 0-105
EPYC 3255 Un­known 25-55 W -40-105
EPYC 3301 February 2018 2 x CCD 12 (12) 4 × 3 2.0 2.15 3.0 32 MB
8 MB per CCX
64 8 × 10GbE DDR4-2666
quad-channel
65 W 0-95
EPYC 3351 12 (24) 1.9 2.75 3.0 SP4 60-80 W 0-105
EPYC 3401 16 (16) 4 × 4 1.85 2.25 3.0 SP4r2 85 W
EPYC 3451 16 (32) 2.15 2.45 3.0 SP4 80-100 W
  1. ^ Core Complexes (CCX) × cores per CCX


Chinese variants[edit]

A variant created for the Chinese server market by an AMD–Chinese joint venture is the Hygon Dhyana system on a chip.[34][35] It is noted to be a variant of the AMD EPYC, and is so similar that "there is little to no differentiation between the chips".[34] It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".[35] Later Benchmarks showed that certain floating point instructions are performing worse and AES is disabled, probably to comply with US export restrictions.[36] Cryptography extensions are replaced by Chinese variants.[37]

References[edit]

  1. ^ Cutress, Ian. "Computex 2017: AMD Press Event Live Blog". www.anandtech.com.
  2. ^ Kampman, Jeff (16 May 2017). "AMD's Naples datacenter CPUs will make an Epyc splash". Tech Report. Retrieved 16 May 2017.
  3. ^ Cutress, Ian (20 June 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". Anandtech.com. Retrieved 12 July 2017.
  4. ^ Paul Alcorn (2021-03-15). "Watch AMD's EPYC 7003 Milan Launch Here". Tom's Hardware. Retrieved 2022-04-05.
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  9. ^ servethehome (2021-11-08). "AMD Bergamo to hit 128 Cores and Genoa at 96 Cores". ServeTheHome. Retrieved 2022-04-05.
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  24. ^ "AMD PS7371BEVGPAF EPYC 7371 3.1GHz 16-Core". www.gamepc.com. Retrieved 2019-01-20.
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  31. ^ "Anandtech's Milan-X article".
  32. ^ "AMDs Exascale-Hammer: Epyc 3 mit 804 MByte Cache, Instinct MI200 mit 47,9 TFlops". c't Magazin (in German). 2021-11-08.
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