FLAGS register

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The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16 bits wide. Its successors, the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller predecessors.

The fixed bits at bit positions 1, 3 and 5, and carry, parity, adjust, zero and sign flags are inherited from an even earlier architecture, 8080 and 8085. The adjust flag used to be called auxiliary carry bit in 8080 and half-carry bit in the Zilog Z80 architecture.


Intel x86 FLAGS register[1]
Bit # Mask Abbreviation Description Category
0 0x0001 CF Carry flag Status
1 0x0002 Reserved, always 1 in EFLAGS [2][3]  
2 0x0004 PF Parity flag Status
3 0x0008 Reserved[3]  
4 0x0010 AF Adjust flag Status
5 0x0020 Reserved[3]  
6 0x0040 ZF Zero flag Status
7 0x0080 SF Sign flag Status
8 0x0100 TF Trap flag (single step) Control
9 0x0200 IF Interrupt enable flag Control
10 0x0400 DF Direction flag Control
11 0x0800 OF Overflow flag Status
12-13 0x3000 IOPL I/O privilege level (286+ only),
always 1[clarification needed] on 8086 and 186
14 0x4000 NT Nested task flag (286+ only),
always 1 on 8086 and 186
15 0x8000 Reserved,
always 1 on 8086 and 186,
always 0 on later models
16 0x0001 0000 RF Resume flag (386+ only) System
17 0x0002 0000 VM Virtual 8086 mode flag (386+ only) System
18 0x0004 0000 AC Alignment check (486SX+ only) System
19 0x0008 0000 VIF Virtual interrupt flag (Pentium+) System
20 0x0010 0000 VIP Virtual interrupt pending (Pentium+) System
21 0x0020 0000 ID Able to use CPUID instruction (Pentium+) System
22-31 0xFFC0 0000 Reserved System
32-63 0xFFFF FFFF...
...0000 0000

Note: The mask column in the table is the AND bitmask (as hexadecimal value) to query the flag(s) within FLAGS register value.


The POPF, POPFD, and POPFQ instructions read from the stack, the first 16, 32, and 64 bits of the flags register, respectively. POPFD was introduced with the i386 architecture and POPFQ with the x64 architecture. In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but not PUSHFD/POPFD.[4]

The following assembly code changes the direction flag (DF):

pushf ; Pushes the current flags onto the stack
pop ax ; Pop the flags from the stack into ax register
push ax ; Push them back onto the stack for storage
xor ax, 400h ; toggle the DF flag only, keep the rest of the flags
push ax ; Push again to add the new value to the stack
popf ; Pop the newly pushed into the FLAGS register
; ... Code here ...
popf ; Pop the old FLAGS back into place

In practical software, the cld and std instructions are used to clear and set the direction flag, respectively. Some instructions in assembly language use the FLAGS register. The conditional jump instructions use certain flags to compute. For example, jz uses the zero flag, jc uses the carry flag and jo uses the overflow flag. Other conditional instructions look at combinations of several flags.

Determination of processor type[edit]

Testing if certain bits in the FLAGS register are changeable allows determining what kind of processor is installed. For example, the alignment flag can only be changed on the 486 and above, so if it can be changed then the CPU is a 486 or higher. These methods of processor detection were not made obsolete by the CPUID instruction introduced with the Intel Pentium, as CPUID is not implemented in these older CPUs.

See also[edit]


  1. ^ Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). 1. May 2012. pp. 3–21.
  2. ^ Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 1. Dec 2016. p. 78.
  3. ^ a b c "Silicon reverse engineering: The 8085's undocumented flags". www.righto.com. Retrieved 2018-10-21.
  4. ^ Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 2B. May 2012. pp. 4–349, 4–432.