The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16 bits wide. Its successors, the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller predecessors.
The fixed bits at bit positions 1 and 3 and carry, parity, zero and sign bits are inherited from an even earlier architecture, 8080. Auxiliary carry bit also retains its position (bit 4), but it used to be called "half-carry bit" in 8080. Interrupt flag has been moved from bit 5 to bit 9, and bit 5 is left unused since then.[dubious ]
|Intel x86 FLAGS register|
|8||TF||Trap flag (single step)||Control|
|9||IF||Interrupt enable flag||Control|
|12-13||IOPL||I/O privilege level (286+ only), always 1 on 8086 and 186||System|
|14||NT||Nested task flag (286+ only), always 1 on 8086 and 186||System|
|15||Reserved, always 1 on 8086 and 186, always 0 on later models|
|16||RF||Resume flag (386+ only)||System|
|17||VM||Virtual 8086 mode flag (386+ only)||System|
|18||AC||Alignment check (486SX+ only)||System|
|19||VIF||Virtual interrupt flag (Pentium+)||System|
|20||VIP||Virtual interrupt pending (Pentium+)||System|
|21||ID||Able to use CPUID instruction (Pentium+)||System|
The POPF, POPFD, and POPFQ instructions read from the stack the first 16, 32, and 64 bits of the flags register, respectively. POPFD was introduced with the i386 architecture and POPFQ with the x64 architecture. In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but not PUSHFD/POPFD.
The following assembly code changes the direction flag (DF):
pushf ; Pushes the current flags onto the stack pop ax ; Pop the flags from the stack into ax register push ax ; Push them back onto the stack for storage xor ax, 400h ; toggle the DF flag only, keep the rest of the flags push ax ; Push again to add the new value to the stack popf ; Pop the newly pushed into the FLAGS register ; ... Code here ... popf ; Pop the old FLAGS back into place
In practical software, the
std instructions are used to clear and set the direction flag, respectively. Some instructions in assembly language use the FLAGS register. The conditional jump instructions use certain flags to compute. For example,
jz uses the zero flag,
jc uses the carry flag and
jo uses the overflow flag. Other conditional instructions look at combinations of several flags.
Determination of processor type
Testing if certain bits in the FLAGS register are changeable allows determining what kind of processor is installed. For example, the alignment flag can only be changed on the 486 and above, so if it can be changed then the CPU is a 486 or higher. These methods of processor detection were not made obsolete by the CPUID instruction introduced with the Intel Pentium, as CPUID is not implemented in these older CPUs.
- Status register
- Flag byte
- Flag (computing)
- Program status word
- Control register
- CPU flag (x86)
- x86 assembly language
- x86 instruction listings
- Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). 1. May 2012. pp. 3–21.
- Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 2B. May 2012. pp. 4–349,4–432.