FMA instruction set
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The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations. There are two variants:
- FMA4 is supported in AMD processors starting with the Bulldozer architecture. FMA4 was realized in hardware before FMA3.
- FMA3 is supported in AMD processors starting with the Piledriver architecture and Intel starting with Haswell processors and Broadwell processors since 2014.
FMA3 and FMA4 instructions have almost identical functionality, but are not compatible. Both contain fused multiply–add (FMA) instructions for floating-point scalar and SIMD operations, but FMA3 instructions have three operands, while FMA4 ones have four. The FMA operation has the form d = round(a · b + c), where the round function performs a rounding to allow the result to fit within the destination register if there are too many significant bits to fit within the destination.
The four-operand form (FMA4) allows a, b, c and d to be four different registers, while the three-operand form (FMA3) requires that d be the same register as a, b or c. The three-operand form makes the code shorter and the hardware implementation slightly simpler, while the four-operand form provides more programming flexibility.
See XOP instruction set for more discussion of compatibility issues between Intel and AMD.
FMA3 instruction set
CPUs with FMA3
- AMD introduced FMA3 support in processors starting with Piledriver architecture for compatibility reasons. The 2nd generation APU processors based on "Trinity" (32nm) supporting FMA3 instructions were launched May 15, 2012. The 2nd generation Bulldozer processors with Piledriver cores supporting FMA3 instructions were launched October 23, 2012.
- Intel introduced hardware FMA3 in processors based on Haswell during 2013.
Excerpt from FMA3
|VFMADD132PDy||ymm, ymm, ymm/m256||a = a·c + b|
|VFMADD132PDx||xmm, xmm, xmm/m128|
|VFMADD132SD||xmm, xmm, xmm/m64|
|VFMADD132SS||xmm, xmm, xmm/m32|
|VFMADD213PDy||ymm, ymm, ymm/m256||a = b·a + c|
|VFMADD213PDx||xmm, xmm, xmm/m128|
|VFMADD213SD||xmm, xmm, xmm/m64|
|VFMADD213SS||xmm, xmm, xmm/m32|
|VFMADD231PDy||ymm, ymm, ymm/m256||a = b·c + a|
|VFMADD231PDx||xmm, xmm, xmm/m128|
|VFMADD231SD||xmm, xmm, xmm/m64|
|VFMADD231SS||xmm, xmm, xmm/m32|
FMA4 instruction set
CPUs with FMA4
- "Heavy Equipment" processors
- Zen: WikiChip's testing shows FMA4 still appears to work (under the conditions of the tests) despite not being officially supported and not even reported by CPUID. This has also been confirmed by Agner. But other tests gave wrong results. AMD Official Web Site FMA4 Support Note ZEN CPUs = AMD ThreadRipper 1900x, R7 Pro 1800, 1700, R5 Pro 1600, 1500, R3 Pro 1300, 1200, R3 2200G, R5 2400G.
- It is uncertain whether future Intel processors will support FMA4, due to Intel's announced change to FMA3.
Excerpt from FMA4
|VFMADDPDx||xmm, xmm, xmm/m128, xmm/m128||a = b·c + d|
|VFMADDPDy||ymm, ymm, ymm/m256, ymm/m256|
|VFMADDPSx||xmm, xmm, xmm/m128, xmm/m128|
|VFMADDPSy||ymm, ymm, ymm/m256, ymm/m256|
|VFMADDSD||xmm, xmm, xmm/m64, xmm/m64|
|VFMADDSS||xmm, xmm, xmm/m32, xmm/m32|
The incompatibility between Intel's FMA3 and AMD's FMA4 is due to both companies changing plans without coordinating coding details with each other. AMD changed their plans from FMA3 to FMA4 while Intel changed their plans from FMA4 to FMA3 almost at the same time. The history can be summarized as follows:
- August 2007: AMD announces the SSE5 instruction set, which includes 3-operand FMA instructions. A new coding scheme (DREX) is introduced for allowing instructions to have three operands.
- April 2008: Intel announces their AVX and FMA instruction sets, including 4-operand FMA instructions. The coding of these instructions uses the new VEX coding scheme, which is more flexible than AMD's DREX scheme.
- December 2008: Intel changes the specification for their FMA instructions from 4-operand to 3-operand instructions. The VEX coding scheme is still used.
- May 2009: AMD changes the specification of their FMA instructions from the 3-operand DREX form to the 4-operand VEX form, compatible with the April 2008 Intel specification rather than the December 2008 Intel specification.
- October 2011: AMD Bulldozer processor supports FMA4.
- January 2012: AMD announces FMA3 support in future processors codenamed Trinity and Vishera; they are based on the Piledriver architecture.
- May 2012: AMD Piledriver processor supports both FMA3 and FMA4.
- June 2013: Intel Haswell processor supports FMA3.
- February 2017 The first generation of AMD Ryzen processors officially supports FMA3, but not FMA4 according to the CPUID instruction. There has been confusion regarding whether FMA4 was implemented or not on this processor due to errata in the initial patch to the GNU Binutils package that has since been rectified. While the FMA4 instructions seem to work according to some tests, they can also give wrong results. Additionally, the initial Ryzen CPUs could be crashed by a particular sequence of FMA3 instructions. It has since been resolved by an updated CPU microcode.
Compiler and assembler support
Different compilers provide different levels of support for FMA4:
- GCC supports FMA4 with -mfma4 since version 4.5.0 and FMA3 with -mfma since version 4.7.0.
- Microsoft Visual C++ 2010 SP1 supports FMA4 instructions.
- Microsoft Visual C++ 2012 supports FMA3 instructions (if the processor also supports AVX2 instruction set extension).
- Microsoft Visual C++ since VC 2013
- PathScale supports FMA4 with -mfma.
- LLVM 3.1 adds FMA4 support, along with preliminary FMA3 support.
- Open64 5.0 adds "limited support".
- Intel compilers support only FMA3 instructions.
- NASM supports FMA3 instructions since version 2.03 and FMA4 instructions since 2.06.
- Yasm supports FMA3 instructions since version 0.8.0 and FMA4 instructions since version 1.0.0.
- FASM supports both FMA3 and FMA4 instructions.
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