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An AND gate with three inputs has a fan-in of 3.

Fan-in is the number of inputs a logic gate can handle.[1] For instance the fan-in for the AND gate shown in the figure is 3.[2] Physical logic gates with a large fan-in tend to be slower than those with a small fan-in. This is because the complexity of the input circuitry increases the input capacitance of the device.[3][4] Using logic gates with higher fan-in will help in reducing the depth of a logic circuit; this is because circuit design is realized by the target logic family at a digital level, meaning any large fan-in logic gates are simply the smaller fan-in gates chained together in series at a given depth to widen the circuit instead.

Fan-in tree of a node refers to a collection of signals that contribute to the input signal of that node.[5]

In quantum logic gates the fan-in always has to be equal to the number of outputs, the Fan-out. Gates for which the numbers of inputs and outputs differ would not be reversible (unitary) and are therefore not allowed.

See also[edit]

  • Fan-out, a related concept, which is the number of inputs that a given logic output drives.


  1. ^ "fan-in and fan-out". Intel. Retrieved 2021-11-12. Fan-in refers to the maximum number of input signals that feed the input equations of a logic cell.
  2. ^ JoCavanagh (21 December 2017). Digital Design and Verilog HDL Fundamentals. CRC Press. pp. 3–. ISBN 978-1-351-83456-8.
  3. ^ Dimitrios Soudris; Peter Pirsch; Erich Barke (29 June 2003). Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation: 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 Proceedings. Springer. pp. 274–. ISBN 978-3-540-45373-4.
  4. ^ Singh Ajay Kumar (30 June 2010). Digital Vlsi Design. PHI Learning Pvt. Ltd. pp. 138–. ISBN 978-81-203-4187-6.
  5. ^ Fan-in tree analysis: a new fault isolation tool. IEEE. doi:10.1109/smelec.1996.616446. Fan-in tree is a collection of subsequent fan-in signals with respect to a given node.