Flash memory controller

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A flash memory controller (or flash controller) manages the data stored on flash memory and communicates with a computer or electronic device. Flash memory controllers can be designed for operating in low duty-cycle environments like SD cards, CompactFlash cards, or other similar media for use in digital cameras, PDAs, mobile phones, etc. USB flash drives use flash memory controllers designed to communicate with personal computers through the USB port at a low duty-cycle. Flash controllers can also be designed for higher duty-cycle environments like solid-state drives (SSD) used as data storage for laptop computer systems clear up to mission-critical enterprise storage arrays.[1]

Flash memory system form factors and governing bodies dictate a lot of characteristics of the Flash memory controller. Conversely, the Flash memory controller characteristics play a major role in the type of application and domain of the memory system.[2]

Initial setup[edit]

After a flash storage device is initially manufactured, the flash controller is first used to format the flash memory. This ensures the device is operating properly, it maps out bad flash memory cells, and it allocates spare cells to be substituted for future failed cells. Some part of the spare cells is also used to hold the firmware which operates the controller and other special features for a particular storage device. A directory structure is created to allow the controller to convert requests for logical sectors into the physical locations on the actual flash memory chips.[1]

Reading, writing, and erasing[edit]

When the system or device needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. Simpler devices like SD cards and USB flash drives typically have a small number of flash memory die connected simultaneously. Operations are limited to the speed of the individual flash memory die. In contrast, a high-performance solid-state drive will have as many as 100 or more dies organized in a matrix with parallel communication paths to enable speeds many times greater than that of a single flash die.[citation needed]

The architecture of NAND Flash means that data can be read and programmed in pages, typically between 4 KB and 16 KB in size, but can only be erased at the level of entire blocks consisting of multiple pages and MB in size.[3]

Wear-leveling and block picking[edit]

Flash memory can withstand a limited number of program-erase cycles. If a particular flash memory block were programmed and erased repeatedly without writing to any other blocks, the one block would wear out before all the other blocks thereby prematurely ending the life of the storage device. For this reason flash controllers use a technique called wear leveling to distribute writes as evenly as possible across all the flash blocks in the SSD. Wear leveling is used to allocate data in such a manner that ensures flash blocks are used equally in terms of consuming their individual write-erase cycle endurance.[4]

In a perfect scenario this would enable every block to be written to its maximum life so they all fail at the same time.[5]

Error Correction Coding[edit]

As NAND Flash cells are prone to errors (especially through use-generated bit errors), a so-called ECC (Error Correction Code) is needed. The ECC unit corrects bit errors and ensures data integrity. Through an array of complex algorithms data from the host is processed through the ECC before being written onto the Flash. A few examples of ECC technologies include Reed Solomon (RS), Bose-Chaudhuri-Hocquenghem (BCH) and Low-Density Parity Check (LDPC).[6]

The effective use of ECC is critical to detecting errors when reading data, whether they are caused by wear, radiation or other disturb effects. Recent ECCs can correct over 100 bit errors within 1K Byte of user data. The required ECC strength depends on the quality of the used Flash technology and is specified by the Flash vendor.

Power-Fail Technology[edit]

Flash Memory Controllers need to avoid corrupted data and failing devices and do so through power-fail technology. Controllers uphold a log of recent Flash transactions to ensure in the event of a black-out or power failure it can recover the last valid entry. It is possible that if a write operation is active during a power-fail situation this data could be lost. [7]

Bad Block Management[edit]

If there are repeated failures in a block or a block fails to erase, it is marked as bad and not be used in future. Flash memories are built with excess spare blocks so they can cope with a certain number of bad blocks before the memory becomes unusable.[8]

Flash Translation Layer (FTL) and Mapping[edit]

Usually, Flash Memory Controller also include the Flash Translation Layer (FTL) a layer below the file system that maps host side or file system logical block addresses (LBAs) to the physical address of the Flash memory (logical-to-physical mapping). The LBAs refer to sector numbers and to a mapping unit of 512 bytes. All LBAs that represent the logical size visible to and managed by the file system are mapped to a physical location (block ID, page ID and sector ID) of the Flash. As part of the wear leveling and other Flash management algorithms (bad block management, read disturb management, safe flash handling etc.), the physical location of an LBA might dynamically change frequently. The mapping units of an FTL can differ so that LBAs are mapped block-, page- or even sub-page-based. Depending on the usage pattern, a finer mapping granularity can significantly reduce the flash wear out and maximize the endurance of a flash based storage media.[9][10][11]

Garbage collection[edit]

Once every block of a solid-state storage device has been written one time, the flash controller will need to return to some of the initial blocks which no longer have current data (also called stale blocks). The data in these blocks were replaced with newly written blocks and now they are waiting to be erased so that new data can be written into them. This is a process called garbage collection (GC). A NAND Flash can only be erased by block. So if data on a single page (within a block) is updated, the page that contained the original data becomes obsolete (garbage) and “holes” of invalid data are generated within the blocks. These blocks still contain valid data on certain pages. When the NAND Flash does not provide any more free blocks to store data, GC is required. This function copies all data which is still valid into new blocks, removing the existing holes in the old blocks.[12]

All SSDs, CF Cards, and other flash storage devices will include some level of garbage collection. The speed at which a flash controller will do this can vary.[13]

Health monitoring[edit]

Tracking the current status and expected the lifetime of the Flash memory is important to avoid unexpected failures and data loss. As with hard disk drives, the standard self-monitoring, analysis and reporting technology (SMART) allows the controller to report the health of the Flash memory and provide early warnings of potential failures well before they occur. [14]

References[edit]

  1. ^ a b "Flash Memory Guide" (PDF). kingston.com. Retrieved 7 March 2013. 
  2. ^ https://www.hyperstone.com Flash Controller Technology - The Fundamentals of Reliable Flash Storage, Retrieved 19. April 2018
  3. ^ https://www.hyperstone.com NAND Flash Controllers - The key to endurance and reliability, Retrieved 7. June 2018
  4. ^ https://www.hyperstone.com Flash Controller Technology - The Fundamentals of Reliable Flash Storage, Retrieved 5. April 2018
  5. ^ Chang, Li-Pin (2007-03-11). "On Efficient Wear Leveling for Large Scale Flash Memory Storage Systems". National ChiaoTung University, HsinChu, Taiwan. CiteSeerX 10.1.1.103.4903Freely accessible. 
  6. ^ https://www.hyperstone.com Flash Controller Technology - The Fundamentals of Reliable Flash Storage, Retrieved 19. April 2018
  7. ^ https://www.hyperstone.com Hyperstone Controller Technology - The Fundamentals of Reliable Flash Storage, Retrieved 19. April 2018
  8. ^ https://www.hyperstone.com Hyperstone Innovation Blog - NAND Flash controllers – The key to endurance and reliability, Retrieved 6. June 2018
  9. ^ http://drona.csa.iisc.ernet.in/~gopi/west10/goodson.pdf
  10. ^ http://flashdba.com/2014/09/17/understanding-flash-the-flash-translation-layer/
  11. ^ http://files.iccmedia.com/magazines/basfeb15/basfeb15-p25.pdf
  12. ^ https://www.hyperstone.com Flash Controller Technology - The Fundamentals of Reliable Flash Storage, Retrieved 5. April 2018
  13. ^ "SSDs - Write Amplification, TRIM and GC" (PDF). OCZ Technology. Retrieved 2010-05-31. 
  14. ^ https://www.hyperstone.com Hyperstone Innovation Blog - NAND Flash controllers – The key to endurance and reliability, Retrieved 6. June 2018