Freescale RS08

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The RS08 [1] core is a reduced-resource version of the Freescale MC68HCS08 central processing unit (CPU), a member of the 6800 microprocessor family. It has been implemented in several microcontroller devices for embedded systems.

Compared to its sibling HC08 and Freescale S08 parts, it has a much-simplified design. The 'R' in its part numbers suggests "Reduced"; Freescale itself describes the core as "ultra-low-end". Typical implementations include fewer on-board peripherals and memory resources, have smaller packages (the smallest is the QFN6 package, at 3mm x 3mm x 1mm), and are priced under US $1. Aims of the simplified design include greater efficiency, greater cost-effectiveness for small-memory-size parts, and smaller die size.

The RS08 employs a von Neumann architecture with shared program and data bus; executing instructions from within data memory is possible. The device is not binary compatible with the S08 core, though the instruction opcodes and addressing modes are a subset of the S08. This allows an easy transition from the S08 core to the RS08 core for designers and engineers.

Short and Tiny addressing modes allow for more efficient access and manipulation of the most-commonly-used variables and registers. These instructions have single-byte instruction opcodes, reducing the amount of program memory required by their frequent use.

Die size is 30% smaller than the S08 core. The RS08 core uses the same bus structure as S08, making memory and peripheral module reuse possible. It offers a Background Debug Mode interface, a single-wire debugging interface that allows interactive control over the processor when installed in a target system.

Devices[edit]

Devices (as of July 2010):

  • MC9RS08KA1: 1 kB of Flash-programmable program memory.
  • MC9RS08KA2: 2 kB of Flash-programmable program memory.
  • MC9RS08LE4: 4 kB of Flash-programmable program memory, SCI.
  • MC9RS08LA8: 8 kB of Flash-programmable program memory, SCI, SPI.
  • MC9RS08KB12: 12 kB of Flash-programmable program memory, I2C, SCI.

Architectural Features[edit]

  • The RS08 core does not manage a stack. During subroutine calls, it preserves a return address in a Shadow Program Counter link register. If a subroutine in turn calls another subroutine, it can preserve the return address in a local variable, call subroutines as necessary, and restore the saved address just before returning.
  • The core's Status register has Carry and Zero flag bits. Overflow and Negative, usually found in other cores, are not present.

Interrupt Handling[edit]

Interrupts are not dispatched through interrupt vectors, as with nearly all other Freescale processors. RS08 interrupts can wake the processor from a WAIT or STOP condition (where execution is temporarily halted), but otherwise do not change program flow. In essence, RS08 runs any thread of programming to completion. The effect is vaguely similar to cooperative multitasking in operating systems.

Though handling external events is synchronous, no overhead due to context switching is required, and low-power operation is possible. Interrupt arbitration is exclusively software-controlled.

Bibliography[edit]

  • Freescale Semiconductor. RS08 Core Reference Manual (RS08RM). Rev. 1.0, 4/2006.
  • Freescale Semiconductor. MC9RS08KA2 Data Sheet (MC9RS08KA2). Rev. 1.0, 4/2006

External links[edit]