Front end of line
|This article needs additional citations for verification. (December 2009) (Learn how and when to remove this template message)|
The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.
FEOL contains all processes of CMOS fabrication needed to form fully isolated CMOS elements:
- Selecting the type of wafer to be used; Chemical-mechanical planarization and cleaning of the wafer.
- Shallow trench isolation (STI) (or LOCOS in early processes, with feature size > 0.25 μm)
- Well formation
- Gate module formation
- Source and drain module formation
- "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)
|This computer hardware article is a stub. You can help Wikipedia by expanding it.|