Front end of line

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BEOL (metalization layer) and FEOL (devices).
CMOS fabrication process

The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.

For the CMOS process, FEOL contains all fabrication steps needed to form fully isolated CMOS elements:

  1. Selecting the type of wafer to be used; Chemical-mechanical planarization and cleaning of the wafer.
  2. Shallow trench isolation (STI) (or LOCOS in early processes, with feature size > 0.25 μm)
  3. Well formation
  4. Gate module formation
  5. Source and drain module formation

See also[edit]

References[edit]

  1. ^ Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8.

Further reading[edit]

  • "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)