Goldmont

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Goldmont
Product code
  • 80668 (Apollo Lake)
  • 80765 (Denverton)
ModelAtom
Transistors14 nm transistors
ArchitectureGoldmont x86
InstructionsMMX, AES-NI, CLMUL
Extensions
PredecessorAirmont (die shrink)
SuccessorGoldmont Plus (optimization)

Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzhen, China, April 2016.[1] The Goldmont architecture borrows heavily from the Skylake Core processors, so it offers a more than 30 percent performance boost compared to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.[2][3]

Design[edit]

Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers.[4] Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake.

The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:

  • An out-of-order execution engine with a 3-wide superscalar pipeline.[5] Specifically:
    • The decoder can decode 3 instructions per cycle.
    • The microcode sequencer can send 3 µops per cycle for allocation into the reservation stations.
    • Retirement supports a peak rate of 3 per cycle.
  • Enhancement in branch prediction which de-couples the fetch pipeline from the instruction decoder.
  • Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
  • Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle (compared to one load or one store per cycle in the Silvermont microarchitecture). The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
  • Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
  • SIMD integer and floating-point instructions execute in a 128-bit wide engine. Throughput and latency of many instructions have improved, including PSHUFB with 1-cycle throughput (versus 5 cycles for Silvermont microarchitecture) and many other SIMD instructions with doubled throughput.
  • Throughput and latency of instructions for accelerating encryption/decryption (AES) and carry-less multiplication (PCLMULQDQ) have been improved significantly in the Goldmont microarchitecture.
  • The Goldmont microarchitecture provides new instructions with hardware accelerated secure hashing algorithm, SHA1 and SHA256.
  • The Goldmont microarchitecture also adds support for the RDSEED instruction for random number generation meeting the NIST SP800-90C standard.
  • PAUSE instruction latency is optimized to enable better power efficiency.

Technology[edit]

Erratum[edit]

Similar to previous Silvermont generation design flaws were found in processor circutry resulting in cease of operation when procesors are actively used for several years. Errata named APL46 "System May Experience Inability to Boot or May Cease Operation"[8] was added to documentation in June 2017 stating that Low pin count, Real time clock, SD card and GPIO interfaces may stop functioning.

Mitigations[9] were found to limit impact on systems. Firmware update for the LPC bus called LPC_CLKRUN# reduces the utilization of the LPC interface which in turn decreases (but not eliminates) LPC bus degradation - some systems are however not compatible with this new firmware. It is recommended not to use SD card as a boot device and to remove the card from the system when not in use, other possible solution being using only UHS-I cards and operating them at 1.8V.

Congatec also states the issues impact USB buses and eMMC, although those are not mentioned in Intel's public documentation. USB should have a maximum of 12% active time and there is a 60TB transmit traffic life expectancy over the lifetime of the port. eMMC should have a maximum of 33% active time and should be set to D3 device low power state by the operating system when not in use.

Newer designs such as Atom C3000 Denverton do not seem to be affected.[10]

List of Goldmont processors[edit]

Desktop processors (Apollo Lake)[edit]

List of desktop processors as follows:[3][11]

Target
segment
Cores
(Threads)
Processor
Branding & Model
GPU Model TDP CPU Clock rate Graphics Clock rate L2
Cache
Release
Date
Price
(USD)
Base Turbo Normal Turbo
Desktop 4 (4) Pentium J4205 Intel HD Graphics 505 (18 EU) 10 W 1.5 GHz 2.6 GHz 250 MHz 800 MHz 2 MB Q3 2016 $161
Celeron J3455 Intel HD Graphics 500 (12 EU) 2.3 GHz 750 MHz $107
2 (2) J3355 2.0 GHz 2.5 GHz 700 MHz

Server processors (Denverton)[edit]

Target
segment
Cores
(Threads)
Processor
Branding & Model
TDP CPU Clock rate L2
Cache
DDR4 Speed Release
Date
Price
(USD)
Base Turbo
Server 16 (16) Atom C3958[12][13] 31 W 2.0 GHz 2.0 GHz 16 MB 2400 Q3 2017 $449
16 (16) C3955[12] 32 W 2.1 GHz 2.4 GHz 16 MB 2400 Q3 2017 $434
12 (12) C3858[12] 25 W 2.0 GHz 2.0 GHz 12 MB 2400 Q3 2017 $332
12 (12) C3850[12] 25 W 2.1 GHz 2.4 GHz 12 MB 2400 Q3 2017 $323
12 (12) C3830[12] 21 W 1.9 GHz 2.3 GHz 12 MB 2133 Q3 2017 $289
12 (12) C3808[12] 25 W 2.0 GHz 2.0 GHz 12 MB 2133 Q3 2017 $369
8 (8) C3758[12] 25 W 2.2 GHz 2.2 GHz 16 MB 2400 Q3 2017 $193
8 (8) C3750[12] 21 W 2.2 GHz 2.4 GHz 16 MB 2400 Q3 2017 $171
8 (8) C3708[12] 17 W 1.7 GHz 1.7 GHz 16 MB 2133 Q3 2017 $209
4 (4) C3558[12] 16 W 2.2 GHz 2.2 GHz 8 MB 2133 Q3 2017 $86
4 (4) C3538[12] 15 W 2.1 GHz 2.1 GHz 8 MB 2133 Q3 2017 $75
4 (4) C3508[12] 11.25 W 1.6 GHz 1.6 GHz 8 MB 1866 Q3 2017 $86
2 (2) C3338[12] 9 W 1.5 GHz 2.2 GHz 4 MB 1866 Q1 2017 $27
2 (2) C3308[12] 9.5 W 1.6 GHz 2.1 GHz 4 MB 1866 Q3 2017 $32

Mobile processors (Apollo Lake)[edit]

List of mobile processors as follows:[3][11]

Target
segment
Cores
(Threads)
Processor
Branding & Model
GPU Model TDP CPU Clock rate Graphics Clock rate L2
Cache
Release
Date
Price
(USD)
Base Turbo Normal Turbo
Mobile 4 (4) Pentium N4200 Intel HD Graphics 505 (18 EU) 6 W 1.1 GHz 2.5 GHz 200 MHz 750 MHz 2 MB Q3 2016 $161
Celeron N3450 Intel HD Graphics 500 (12 EU) 2.2 GHz 700 MHz $107
2 (2) N3350 2.4 GHz 650 MHz

Embedded processors (Apollo Lake)[edit]

List of embedded processors as follows:

Target
segment
Cores
(Threads)
Processor
Branding & Model
GPU Model TDP CPU Clock rate Graphics Clock rate L2
Cache
Release
Date
Price
(USD)
Base Turbo Normal Turbo
Embedded 4 (4) Atom x7 E3950 Intel HD Graphics 505 (18 EU) 12 W 1.6 GHz 2.0 GHz 500 MHz 650 MHz 2 MB Q3 2016
Atom x5 E3940 Intel HD Graphics 500 (12 EU) 9.5 W 1.8 GHz 400 MHz 600 MHz
2 (2) E3930 6.5 W 1.3 GHz 550 MHz

Automotive processors (Apollo Lake)[edit]

There is also an Atom A3900 series exclusively for automotive customers with AEC-Q100 qualification[14]:

Target
segment
Cores
(Threads)
Processor
Branding & Model
GPU Model TDP CPU Clock rate Graphics Clock rate L2
Cache
Release
Date
Price
(USD)
Base Turbo Normal Turbo
Automotive 4 (4) Atom x7 A3960 Intel HD Graphics 505 (18 EU) 12.5 W 1.9 GHz 2.4 GHz 600 MHz 750 MHz 2 MB
A3950 9.5 W 1.6 GHz 2.0 GHz 500 MHz 650 MHz
Atom x5 A3940 Intel HD Graphics 500 (12 EU) 8 W 1.8 GHz 400 MHz 600 MHz
2 (2) A3930 6 W 1.3 GHz 550 MHz

Tablet processors (Willow Trail)[edit]

Willow Trail platform was canceled. Apollo Lake will be offered instead.[15]

See also[edit]

References[edit]

  1. ^ Eric Brown (2016-04-18). ""Apollo Lake" Atoms to offer graphics-rich Goldmont cores". Hackerboards.com. Retrieved 2016-06-11.
  2. ^ Anton Shilov (2016-04-15). "Intel Unveils New Low-Cost PC Platform: Apollo Lake with 14nm Goldmont Cores". Anandtech.com. Retrieved 2016-06-11.
  3. ^ a b c Alexander Fagot/ Allen Ngo (2016-06-07). "Intel claims Apollo Lake will be 30 percent faster than Braswell". Notebookcheck.net. Retrieved 2016-06-11.
  4. ^ Anton Shilov (2015-06-10). "Intel preps 'Apollo Lake' CPUs with 'Goldmont' cores, Gen9 graphics". Retrieved 2016-06-11.
  5. ^ Kanter, David. "Goldmont Takes Atom to 14nm". The Linley Group. The Linley Group. Retrieved 17 August 2017.
  6. ^ https://downloadmirror.intel.com/28289/eng/ReleaseNotes_25.20.100.6373.pdf
  7. ^ "Mesa 13.0 Released With Intel OpenGL 4.5, RADV Radeon Vulkan Driver - Phoronix". www.phoronix.com.
  8. ^ "Intel® Pentium® and Celeron® Processor N- and J- Series Specification Update" (PDF). Retrieved 2018-04-13.
  9. ^ "Errata sheet - congatec Apollo Lake designs" (PDF). congatec. 2017-07-26.
  10. ^ "Intel® Atom® Processor C3000 Product Family Specification Update" (PDF). Retrieved 2018-04-13.
  11. ^ a b Gennadiy Shvets (2016-06-09). "Model numbers of Apollo Lake processors revealed". cpu-world.com. Retrieved 2016-06-11.
  12. ^ a b c d e f g h i j k l m n Kennedy, Patrick (15 August 2017). "Intel Atom C3000 Series Launch SKUs and Differentiation". Serve the Home. Retrieved 15 August 2017.
  13. ^ Cutress, Ian (15 August 2017). "More Denverton Noise: Gigabyte's MA1-ST0 Features Unannounced 16-Core C3958". Anandtech. Retrieved 15 August 2017.
  14. ^ "Intel Atom® Processor E3900 and A3900 Series Datasheet Addendum" (PDF). Intel. Retrieved 12 January 2018.
  15. ^ Ryan Smith & Ian Cutress (2016-04-29). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Cancelled". Anandtech.com.