I²S

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Not to be confused with I²C.
I²S
Type Bus
Designer Philips Semiconductor, known today as NXP Semiconductors
Designed 1986; 30 years ago (1986)
Data signal Push-Pull
Width 1 data line (SD) +
2 clock lines (SCK, WS)
Protocol Serial

I²S (Inter-IC Sound), pronounced I-squared-S, is an electrical serial bus interface standard used for connecting digital audio devices together. It is used to communicate PCM audio data between integrated circuits in an electronic device. The I²S bus separates clock and serial data signals, resulting in a lower jitter than is typical of communications systems that recover the clock from the data stream. Alternatively I²S is spelled I2S (pronounced I-two-S) or IIS (pronounced I-I-S). Despite the name, it is unrelated to the bidirectional I²C bus.

History[edit]

This standard was introduced in 1986 by Philips (now NXP) and was last revised in 1996.[1]

Details[edit]

The I²S protocol outlines one specific type of PCM digital audio communication with defined parameters outlined in the Philips specification.

The bus consists of at least three lines:

  1. Bit clock line
    • Officially "continuous serial clock (SCK)".[1] Typically written "bit clock (BCLK)".[2]
  2. Word clock line
    • Officially "word select (WS)".[1] Typically called "left-right clock (LRCLK)".[2]
  3. At least one multiplexed data line
    • Officially "serial data (SD)",[1] but can be called SDATA, SDIN, SDOUT, DACDAT, ADCDAT, etc.[2]

It may also include the following lines:

  1. Master clock (typically 256 x LRCLK)
    • This is not part of the I2S standard,[3] but is commonly included for synchronizing the internal operation of the analog/digital converters.[4][5]
  2. A multiplexed data line for upload

The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency is the product of the sample rate, the number of bits per channel and the number of channels. So, for example, CD Audio with a sample frequency of 44.1 kHz, with 16 bits of precision and two channels (stereo) has a bit clock frequency of:

44.1 kHz × 16 × 2 = 1.4112 MHz

The word select clock lets the device know whether channel 1 or channel 2 is currently being sent, since I²S allows two channels to be sent on the same data line. It is a 50% duty-cycle signal that has the same frequency as the sample frequency. For stereo material, the I²S specification states that left audio is transmitted on the low cycle of the word select clock and the right channel is transmitted on the high cycle.

Data is signed, encoded as two's complement with the MSB (most significant bit) first.[1]:2

In audio equipment the I²S sometimes forms an external link between the CD transport and a separate DAC box, contrary to purely internal connection within one player box. This may form an alternative to the commonly used AES/EBU or Toslink or S/PDIF standards. There is no standard interconnecting cable for this application. Some manufacturers provide simply three BNC connectors, an 8P8C ("RJ45") socket or a DE-9 connector. Others like Audio Alchemy (now defunct) used DIN connectors.

See also[edit]

References[edit]

  1. ^ a b c d e I²S bus specification (PDF), Philips Semiconductors, October 1986, archived from the original (PDF) on July 2, 2006 
  2. ^ a b c Lewis, Jerad (January 2012). "Technical Article MS-2275: Common Inter-IC Digital Interfaces for Audio Data Transfer" (PDF). Analog Devices, Inc. 
  3. ^ "PCM1781 (or any I2S DAC) clock sources - Audio Converters Forum - Audio Converters - TI E2E Community". e2e.ti.com. Retrieved 2016-11-04. True, the master (modulator) clock is not part of the I2S standard 
  4. ^ "MCLK in I2S audio protocol". electronics.stackexchange.com. Retrieved 2016-11-04. Clock source for the delta-sigma modulators and digital filters. ... It is the clock that is used by the audio codec ... to time and/or drive its own internal operation. 
  5. ^ Arbona, Jorge (September 2010). "Application Report SLAA469 Audio Serial Interface Configurations for Audio Codecs" (PDF). Audio converters based on the delta-sigma (ΔΣ) architecture require an internal master clock that operates at a much faster rate than the target sample rate. 

External links[edit]