IBM System/4 Pi

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search
The IBM AP-101S Space Shuttle General Purpose Computer is a member of the System/4 Pi family

The IBM System/4 Pi is a family of avionics computers used, in various versions, on the F-15 Eagle fighter, E-3 Sentry, AWACS, Harpoon Missile, NASA's Skylab, MOL, and the Space Shuttle, as well as other aircraft. The name of the system refers to the number of steradians (4π) in a sphere.[1] Development began in 1965, deliveries in 1967.[2]

It descends from the approach used in the System/360 mainframe family of computers in that members of the family were intended for use in many varied user applications. Previously custom computers had been designed for each aerospace application, which was extremely costly.


System/4 Pi consisted of basic models:[3][4]

  • Model TC (Tactical Computer)[5][6] - A briefcase-size computer for applications such as missile guidance, helicopters, satellites and submarines. Weight: about 18 pounds (8.2 kg)
  • Model CP (Customized Processor/Cost Performance)[7][8] - An intermediate-range processor for applications such as aircraft navigation, weapons delivery, radar correlation and mobile battlefield systems. Weight: 80 pounds (36 kg) total[9]
    • Model CP-2 (Cost Performance - Model 2), weight 47 pounds (21 kg)[10]
  • Model EP (Extended Performance)[11][12] - A large-scale data processor for applications requiring real-time processing of large volumes of data, such as manned spacecraft, airborne warning and control systems and command and control systems. Weight: 75 pounds (34 kg)

System/360 connections[edit]

Connections with System/360:[13]

  • main storage arrays of System/4 Pi were assembled from core planes that were militarized versions of those used in IBM System/360 computers
  • software was for both 360 and 4 Pi
  • Model EP used an instruction subset of IBM System/360[14] (Model 44)[15] - user programs could be checked on System/360


The Skylab space station employed the model TC-1,[16] which had a 16-bit word length and 16,384 words of memory with a custom input/output assembly.[17]

The top-of-the-line 4 Pi is the AP-101, used in the AWACS. The U.S. Navy used a similar variant, the AN/ASQ-155, in the carrier based A-6E/A-6E TRAM medium attack aircraft. The Shuttle is controlled by five AP-101 computers, three of which are arranged in a Triple Modular Redundant configuration, one was kept powered up as a "hot spare" and one was maintained powered down as a redundant "cold spare".


The AP-101, being the top-of-the-line of the System/4 Pi range, shares its general architecture with the System/360 mainframes.[18] It has 16 32-bit registers, and uses a microprogram to define an instruction set of 154 instructions. Originally only 16 bits were available for addressing memory; later this was extended with four bits from the program status word register, allowing a directly addressable memory range of 1M locations. This avionics computer has been used in the U.S. Space Shuttle, the B-52 and B-1B bombers,[18] and other aircraft. It is a repackaged version of the AP-1 used in the F-15 fighter.[19] When it was designed, it was a high-performance pipelined processor with core memory. While today its specifications are exceeded by most of the modern microprocessors, it was considered high-performance for its era as it could process 480,000 instructions per second (compared to the 7,000 instructions per second of the computer used on Gemini spacecraft).[18] It remains in service (formerly on the Space Shuttle) because it works and is flight-certified, whereas a new certification would be too expensive. The Space Shuttle AP-101s were augmented by glass cockpit technology.

The B-1B bomber employs a network of eight model AP-101F computers.[20]

Semiconductor memory board from an IBM AP-101S Space Shuttle General Purpose Computer.

The AP-101B originally used in the Shuttle had core memory. The AP-101S upgrade in the early 1990s used semiconductor memory.[21] Each AP-101 on the Shuttle was coupled with an Input-Output Processor (IOP), consisting of one Master Sequence Controller (MSC) and 24 Bus Control Elements (BCEs). The MSC and BCEs executed programs from the same memory system as the main CPU, offloading control the Shuttle's serial data bus system from the CPU.

The Space Shuttle used five AP-101 computers as general-purpose computers (GPCs). Four operated in sync, for redundancy, while the fifth was a backup running software written independently. The Shuttle's guidance, navigation and control software was written in HAL/S, a special-purpose high-level programming language, while much of the operating system and low-level utility software was written in assembly language. AP-101s used by the US Air Force are mostly programmed in JOVIAL, such as the system found on the B-1B Lancer bomber.[22]


  1. ^ IBM 1967, Foreword, p. iii/iv (6).
  2. ^ IBM 1967, p. 1-3 (9).
  3. ^ IBM 1967.
  4. ^ Bedford, D. P.; Markarian, H.; Pleszkoch, N. L. (Mar 1967). "Appendix E: SYSTEM 4 Pi COMPUTER CHARACTERISTICS". Study of control computers for control moment gyro stability and control systems. Volume I - Engineering. Model TC and CP-2. pp. E-1 - E-21 (126-147).
  5. ^ IBM 1967, Section 2: Model TC, pp. 2-1 - 2-13/2-14 (20-32).
  6. ^ IBM & Overview, Model TC, pp. -2-13 (1-16).
  7. ^ IBM 1967, Section 3: Model CP, pp. 3-1 - 3-9/3-10 (33-41).
  8. ^ IBM & Overview, Model CP, pp. -3-15 (17-35).
  9. ^ IBM & Overview, Model CP, p. 3 (23).
  10. ^ IBM & Overview, Model CP-2, pp. -2-13 (36-51).
  11. ^ IBM 1967, Section 4: Model EP, pp. 4-1 - 4-13/4-14 (42-54).
  12. ^ IBM & Overview, Model EP, pp. -2-18 (52-72).
  13. ^ IBM 1967, pp. 1-7, 1-12 - 1-13/1-14, 4-3 (13, 18-19, 44).
  14. ^ "1.1 System/360 Compatibility and 2.2 System/360 Compatibility". System/4 Pi Engineering Description: Model EP. Owego, NY: Federal Systems Division of IBM. 1966. pp. 1, 4-5 (6, 9-10).
  15. ^ IBM & Overview, Model EP: Summary, p. 2 (56).
  16. ^ Jenkins, Dennis (April 5, 2001). "Advanced Vehicle Automation and Computers Aboard the Shuttle". NASA History Homepage. NASA. Retrieved 27 October 2013.
  17. ^ "Skylab Space Station". eoPortal. ESA. Retrieved 27 October 2013.
  18. ^ a b c "Computers in Spaceflight: The NASA Experience". Chapter Four - Computers in the Space Shuttle Avionics System - The DPS hardware configuration. Retrieved 2018-11-15.
  19. ^ Computers in Spaceflight: The NASA Experience - Chapter Four - Computers in the Space Shuttle Avionics System
  20. ^ Stormont, D.P.; Welgan, R. (23–27 May 1994). "Risk management for the B-1B computer upgrade". Proceedings of National Aerospace and Electronics Conference (NAECON'94). 2: 1143–1149. doi:10.1109/NAECON.1994.332913.
  21. ^ Norman, P. Glenn (1987), "The new AP101S General-Purpose Computer (GPC) for the Space Shuttle", IEEE Proceedings, 75 (3): 308–319, doi:10.1109/PROC.1987.13738
  22. ^ Jovial to smooth U.S. Air Force shift to Ada. (processing language)


External links[edit]