IBM z14 (microprocessor)
|History of IBM mainframes, 1952–present|
|Max. CPU clock rate||5.2 GHz|
|Min. feature size||14 nm|
|L1 cache||128 KB I-L1|
128 KB D-L1
|L2 cache||2 MB I-L2|
4 MB D-L2
|L3 cache||128 MB|
The z14 is a microprocessor made by IBM for their IBM Z mainframe computers, announced on July 17, 2017. Manufactured at GlobalFoundries' East Fishkill, New York fabrication plant. IBM stated that it is the world's fastest microprocessor by clock rate at 5.2 GHz, with a 10% increased performance per core and 30% for the whole chip compared to its predecessor the z13.
The Processor Unit chip (PU chip) has an area of 696 mm2 (25.3 × 27.5 mm) and consists of 6.1 billion transistors. It is fabricated using GlobalFoundries' 14 nm FinFET silicon on insulator fabrication process, using 17 layers of metal and supporting speeds of 5.2 GHz, which is higher than its predecessor, the z13. The PU chip has 10 cores but can have 7–10 cores (or "processor units" in IBM's parlance) enabled depending on configuration. The z14 cores supports two-way simultaneous multithreading for more applications than previously available.
The PU chip is packaged in a single-chip module, which is the same as its predecessor, but a departure from previous designs which were mounted on large multi-chip modules. A computer drawer consists of six PU chips and one Storage Controller (SC) chip containing the L4 cache.
The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline. New in z14 is a cryptographic coprocessor, called CPACF, attached to each core, used for random number generation, hashing, encryption and decrypting and compression. Further enhancements include an optimization of the core's pipeline, doubling the on-chip caches, better branch prediction, a new decimal arithmetic SIMD engine designed to boost COBOL and PL/I code, a "guarded storage facility" that helps Java applications during garbage collection, and other enhancements that increase the cores' performance compared to the predecessors.
The instruction pipeline has an instruction queue that can fetch 6 instructions per cycle; and issue up to 10 instructions per cycle. Each core has a private 128 KB L1 instruction cache, a private 128 KB L1 data cache, a private 2 MB L2 instruction cache, and a private 4 MB L2 data cache. In addition, there is a 128 MB shared L3 cache implemented in eDRAM.
The z14 chip has on board multi-channel DDR4 RAM memory controller supporting a RAID-like configuration to recover from memory faults. The z14 also includes two GX bus as well as two new Gen 3 PCIe controllers for accessing host channel adapters and peripherals. The PU chips has three X-buses for communications to three neighboring PU chips and the SC chip.
A compute drawer consists of two sets of three PU chips and one Storage Controller chip (SC chip). Even though each PU chip has 128 MB L3 cache shared by the 10 cores and other on-die facilities, the SC chip adds 672 MB off-die eDRAM L4 cache shared by the six PU chips in the drawer. The SC chips also handle the communications between the sets of three PU in the drawer as well as communications between drawers using the A-Bus. The SC chip is manufactured on the same 14 nm process as the z14 PU chips, has 17 metal layers, similarly measures 25.3 × 27.5 mm (696 mm2), but consists of 9.7 billion transistors due to amount of L4 memory and runs at half the clock frequency of the PU chip.