The IEEE 1164 standard defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description. It was sponsored by the Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers (IEEE). The standardization effort was based on the donation of the Synopsys MVL-9 type declaration.
The primary data type std_ulogic (standard unresolved logic) consists of nine character literals in the following order:
||strong drive, unknown logic value|
||strong drive, logic zero|
||strong drive, logic one|
||weak drive, unknown logic value|
||weak drive, logic zero|
||weak drive, logic one|
This system promoted a useful set of logic values that typical CMOS logic designs could implement in the vast majority of modeling situations. The
'Z' literal makes tri-state buffer logic easy. The
'L' weak drives permit wired-AND and wired-OR logic. Additionally, the
'U' state is the default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary.
In VHDL, the hardware designer makes the declarations visible via the following
library IEEE; use IEEE.std_logic_1164.all;
Using values in simulation
Many hardware description language (HDL) simulation tools, such as Verilog and VHDL, support an unknown value like that shown above during simulation of digital electronics. The unknown value may be the result of a design error, which the designer can correct before synthesis into an actual circuit. The unknown also represents uninitialised memory values and circuit inputs before the simulation has asserted what the real input value should be.
HDL synthesis tools usually produce circuits that operate only on binary logic.
When designing a digital circuit, some conditions may be outside the scope of the purpose that the circuit will perform. Thus, the designer does not care what happens under those conditions. In addition, the situation occurs that inputs to a circuit are masked by other signals so the value of that input has no effect on circuit behaviour.
In these situations, it is traditional to use
'X' as a placeholder to indicate "Don't Care" when building truth tables. This is especially common in state machine design and Karnaugh map simplification. The
'X' values provide additional degrees of freedom to the final circuit design, generally resulting in a simplified and smaller circuit.
Once the circuit design is complete and a real circuit is constructed, the
'X' values will no longer exist. They will become some tangible
'1' value but could be either depending on the final design optimisation.
Some digital devices support a form of three-state logic on their outputs only. The three states are "0", "1", and "Z".
Commonly referred to as tristate  logic (a trademark of National Semiconductor), it comprises the usual true and false states, with a third transparent high impedance state (or 'off-state') which effectively disconnects the logic output. This provides an effective way to connect several logic outputs to a single input, where all but one are put into the high impedance state, allowing the remaining output to operate in the normal binary sense. This is commonly used to connect banks of computer memory and other similar devices to a common data bus; a large number of devices can communicate over the same channel simply by ensuring only one is enabled at a time.
It is important to note that while outputs can have one of three states, inputs can only recognise two. Hence the kind of relations shown in the table above do not occur. Although it could be argued that the high-impedance state is effectively an "unknown", there is absolutely no provision in the vast majority of normal electronics to interpret a high-impedance state as a state in itself. Inputs can only detect "0" and "1".
When a digital input is left disconnected (i.e., when it is given a high impedance signal), the digital value interpreted by the input depends on the type of technology used. TTL technology will reliably default to a "1" state. On the other hand, CMOS technology will temporarily hold the previous state seen on that input (due to the capacitance of the gate input). Over time, leakage current causes the CMOS input to drift in a random direction, possibly causing the input state to flip. Disconnected inputs on CMOS devices can pick up noise, they can cause oscillation, the supply current may dramatically increase (crowbar power) or the device may completely destroy itself.
- 1164-1993 – IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Stdlogic1164). 1993. doi:10.1109/IEEESTD.1993.115571. ISBN 0-7381-0991-6.
- D. Michael Miller; Mitchell A. Thornton (2008). Multiple valued logic: concepts and representations. Synthesis lectures on digital circuits and systems. 12. Morgan & Claypool Publishers. ISBN 978-1-59829-190-2.