The IEEE 1164 standard defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description. It was sponsored by the Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers (IEEE). The standardization effort was based on the donation of the Synopsys MVL-9 type declaration.
The primary data type std_ulogic (standard unresolved logic) consists of nine character literals in the following order:
|'X'||strong drive, unknown logic value|
|'0'||strong drive, logic zero|
|'1'||strong drive, logic one|
|'W'||weak drive, unknown logic value|
|'L'||weak drive, logic zero|
|'H'||weak drive, logic one|
This system promoted a useful set of logic values that typical CMOS logic designs could implement in the vast majority of modeling situations. The 'Z' literal makes tri-state buffer logic easy. The 'H' and 'L' weak drives permit wired-AND and wired-OR logic. Additionally, the 'U' state is the default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary.
In VHDL, the hardware designer makes the declarations visible via the following
library IEEE; use IEEE.std_logic_1164.all;
- "VHDL and Logic Synthesis". Retrieved 22 January 2010.
- 1164-1993 – IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Stdlogic1164). 1993. doi:10.1109/IEEESTD.1993.115571. ISBN 0-7381-0991-6.
- D. Michael Miller; Mitchell A. Thornton (2008). Multiple valued logic: concepts and representations. Synthesis lectures on digital circuits and systems 12. Morgan & Claypool Publishers. ISBN 978-1-59829-190-2.