Interrupt request (PC architecture)
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In a computer, an interrupt request (or IRQ) is a hardware signal sent to the processor that temporarily stops a running program and allows a special program, an interrupt handler, to run instead. Interrupts are used to handle such events as data receipt from a modem or network, key presses or mouse movements, and operating system timer requests to switch from process execution into kernel mode.
Interrupt lines are often identified by an index with the format of IRQ followed by a number. For example, on the Intel 8259 family of PICs there are eight interrupt inputs commonly referred to as IRQ0 through IRQ7. In x86 based computer systems that use two of these PICs, the combined set of lines are referred to as IRQ0 through IRQ15. Technically these lines are named IR0 through IR7, and the lines on the ISA bus to which they were historically attached are named IRQ0 through IRQ15
Newer x86 systems integrate an Advanced Programmable Interrupt Controller (APIC) that conforms to the Intel APIC Architecture. These APICs support a programming interface for up to 255 physical hardware IRQ lines per APIC, with a typical system implementing support for only around 24 total hardware lines.
When working with personal computer hardware, installing and removing devices, the system relies on interrupt requests. There are default settings that are configured in the system BIOS and recognized by the operating system. These default settings can be altered by advanced users. Modern plug and play technology has not only reduced the need for concern for these settings, but has also virtually eliminated manual configuration.
Typically, on systems using the Intel 8259, 16 IRQs are used. IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259 PIC. The first PIC, the master, is the only one that directly signals the CPU. The second PIC, the slave, instead signals to the master on its IRQ 2 line, and the master passes the signal on to the CPU. There are therefore only 15 interrupt request lines available for hardware.
On newer systems using the Intel APIC Architecture, typically there are 24 IRQs available, and the extra 8 IRQs are used to route PCI interrupts, avoiding conflict between dynamically configured PCI interrupts and statically configured ISA interrupts. On early APIC systems with only 16 IRQs or with only Intel 8259 interrupt controllers, PCI interrupt lines were routed to the 16 IRQs using a PIR integrated into the southbridge.
The easiest way of viewing this information on Microsoft Windows is to use Device Manager or System Information (msinfo32.exe). On Linux, IRQ mappings can be viewed by executing cat /proc/interrupts or using the procinfo utility.
- IRQ 0 – system timer (cannot be changed)
- IRQ 1 – keyboard controller (cannot be changed)
- IRQ 2 – cascaded signals from IRQs 8–15 (any devices configured to use IRQ 2 will actually be using IRQ 9)
- IRQ 3 – serial port controller for serial port 2 (shared with serial port 4, if present)
- IRQ 4 – serial port controller for serial port 1 (shared with serial port 3, if present)
- IRQ 5 – parallel port 2 and 3 or sound card
- IRQ 6 – floppy disk controller
- IRQ 7 – parallel port 1. It is used for printers or for any parallel port if a printer is not present. It can also be potentially be shared with a secondary sound card with careful management of the port.
- IRQ 8 – real-time clock (RTC)
- IRQ 9 – Advanced Configuration and Power Interface system control interrupt on Intel chipsets. Other chipset manufacturers might use another interrupt for this purpose, or make it available for the use of peripherals (any devices configured to use IRQ 2 will actually be using IRQ 9)
- IRQ 10 – The Interrupt is left open for the use of peripherals (open interrupt/available, SCSI or NIC)
- IRQ 11 – The Interrupt is left open for the use of peripherals (open interrupt/available, SCSI or NIC)
- IRQ 12 – mouse on PS/2 connector
- IRQ 13 – CPU co-processor or integrated floating point unit or inter-processor interrupt (use depends on OS)
- IRQ 14 – primary ATA channel
- IRQ 15 – secondary ATA channel (ATA interface usually serves hard disks and CD drives)
In early IBM-compatible personal computers, an IRQ conflict is a once common hardware error, received when two devices were trying to use the same interrupt request (or IRQ) to signal an interrupt to the Programmable Interrupt Controller (PIC). The PIC expects interrupt requests from only one device per line, thus more than one device sending IRQ signals along the same line will generally cause an IRQ conflict that can freeze a computer.
For example, if a modem expansion card is added into a system and assigned to IRQ4, which is traditionally assigned to the serial port 1, it will likely cause an IRQ conflict. Initially, IRQ 7 was a common choice for the use of a sound card, but later IRQ 5 was used when it was found that IRQ 7 would interfere with the printer port (LPT1). The serial ports are frequently disabled to free an IRQ line for another device. IRQ 2/9 is the traditional interrupt line for an MPU-401 MIDI port, but this conflicts with the ACPI system control interrupt (SCI is hardwired to IRQ9 on Intel chipsets); this means ISA MPU-401 cards with a hardwired IRQ 2/9, and MPU-401 device drivers with a hardcoded IRQ 2/9, cannot be used in interrupt-driven mode on a system with ACPI enabled.
In some rare conditions, two devices could share the same IRQ as long as they were not used simultaneously. To solve this problem, the later PCI bus specification allows for IRQ sharing, with the additional support for Message Signaled Interrupts (MSI) in its later revisions. PCI Express does not have physical interrupt lines at all, and uses MSI exclusively.
Serialized interrupts are transmitted over a single-line bus with the help of a clock. A time slot is dedicated to each device, the initial synchronization being done by the host. As a simplified example:
- the host drives the SERIRQ line low for seven clocks, then high for another
- if device #6 needs to send an interrupt requests, it waits for 6*3=18 clocks, then drives SERIRQ low for a clock and high for another
The devices can synchronize at the first step because the line can only be driven low for two or more consecutive clocks by the host: no other device drives it low for more than one clock. The host recognizes the sources of the interrupts by watching the line while counting the number of clocks: if it sees the SERIRQ line being driven low at the eighteenth clock, then device 18/3=6 requested interruption.
The above is the continuous mode, where the host initiates the protocol. In the quiet mode, a device requests interruption by driving SERIRQ low for a clock. The host then continues driving the line low for the other six clocks. From this point on, the protocol is the same. In both modes, the number of clocks of the initial synchronization packet may range from four to eight.
At the beginning, the protocol works in continuous mode. At the end of each complete bus transaction (after the host has driven SERIRQ low and then waited for all devices to send interrupt requests) the host sends a final message: it drives the SERIRQ line low for two or three packets depending on the mode that will be used in the next transaction.
Since the clock may already be available (e.g., the PCI clock) the number of lines needed for interrupt requests reduces from the number of devices to one, the single SERIRQ line.
- Oshins, Jake (December 30, 2001). "RE: ACPI Machines and IRQ 9 [was: Communicating with the NT developers]". Retrieved April 17, 2014.
- "Serialized IRQ Support for PCI Systems, Revision 6.0" (PDF).
- Gilluwe, Frank van. The Undocumented PC, Second Edition, Addison-Wesley Developers Press, 1997. ISBN 0-201-47950-8
- Shanley, Tom. ISA System Architecture, Third Edition, Addison-Wesley Publishing Company, 1995. ISBN 0-201-40996-8
- Solari, Edward. PCI & PCI-X Hardware and Software Architecture & Design, Sixth Edition, Research Tech Inc., 2004. ISBN 0-9760865-0-6
- IRQ interrupt request
- Expansion Bus Configuration
- IA-32 Intel Architecture Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1 – more information on the Intel 8259 PIC and its IRQ lines
- Ralf Brown's Interrupt List