Ian A. Young

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Ian A. Young
Ian Young Intel Senior Fellow Picture.jpg
Born
ResidencePortland, Oregon
CitizenshipUnited States, Australia
Alma materUniversity of California, Berkeley, University of Melbourne, Australia
Known forphase-locked loop
AwardsFellow, IEEE 1999; Fellow Intel 1996, Senior Fellow Intel 2004
Scientific career
InstitutionsIntel, University of California, Berkeley, Mostek
ThesisMOS switched-capacitor analogue sampled-data recursive filters (1978)
Doctoral advisorDavid A. Hodges, Paul R. Gray

Ian A. Young is an Intel manager.[1] He was a manager of the design for an oscillator used in Intel microprocessors which led to the scaling of the clock rates from 30 MHz to 3 GHz, ushering in the GHz computing era. (dubious claim, please cite proper reference since this was a common achievement of university and industry )[2]

Young was a co-inventor on the Intel BiCMOS logic circuit family,[3][4] adopted in Pentium, Pentium Pro, Pentium II microprocessors.

Young has written 50 research papers,[5] and has 71 patents[6] in switched capacitor circuits, DRAM, SRAM, BiCMOS, x86 clocking, Photonics and spintronics.

Biography[edit]

Born in Melbourne, Australia, Young received his bachelor's and master's degrees in electrical engineering from the University of Melbourne, Australia. He received his PhD in electrical engineering from the University of California, Berkeley in 1978, where he did research on MOSFET switched-capacitor filters.[7]

Technical career[edit]

Early career, analog MOS integrated circuits and switched capacitor filters[edit]

Young obtained his PhD from University of California, Berkeley in 1978, working with David A. Hodges, developing the first switched MOS capacitor circuits which later developed into analogue MOS switched capacitor filters.[7][8]

Intel BiCMOS for Logic and SRAM[edit]

Young started at Intel in 1983 with the development of circuits for the world's first 1 Mb DRAM in 1 μm CMOS in 1985,[9] and first 64 K SRAM in 1 μm CMOS. This was also the first military qualified SRAM under the VHIC program.[10] At 600 nanometre node, Intel adopted BiCMOS for logic requiring the development of a BiCMOS SRAM for cache and a new family of standard logic circuits.The BiCMOS logic family employed the npn devices in the pull-up path of the BiCMOS gate, to form a low power CMOS logic family with high capacitive drive capability. Intel's BiCMOS technology was enabled by an innovative triple diffused npn transistor. This led to a highly manufacturable low cost process due to minimum number of additional process steps. In contrast, other companies employed BiCMOS to implement emitter-coupled logic for microprocessors, which consumed much more power. The BiCMOS circuits were developed for the Pentium processor family and its follow-on generations, Pentium Pro, Pentium II processor family.

Pentium era and clock scaling[edit]

Young developed the original Phase Locked Loop (PLL) based clocking circuit in a microprocessor while working on the 50 MHz Intel 80486 processor design. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel microprocessors through the 0.13 μm 3.2 GHz Pentium 4. The successful introduction of GHz clocking contributed to massive improvements in computing power.

The 486DX2 architecture showing on board PLL and clock
Intel CPU clock scaling

The integration of an on-chip PLL enabled the clock rates to exceed the off chip interconnect I/O rate in DX2. This led to the integration of an on-chip cache, paving the path for the first microprocessor with 1 million transistors.

The clock rate scaling ushered by Intel and AMD ended as the thermal power dissipation of processors reached 100 W/cm^2. By the end of the race for clock speed, the clock rates had increased by a factor of more than 50. Intel subsequently shifted to multi-core era with modified Intel Core architecture and concurrent improvements in cache sizes to take advantage of the continued success of Moore's law.

Interconnects and photonics[edit]

In 2001, as single end signalled aluminium interconnects[11] reached the technology scaling limits, Young and co-workers quantified the migration to repeated electrical interconnects for mainstream microprocessors.

Beyond CMOS computing[edit]

He oversaw Dr. Dmitri Nikonov et al. for a uniform bench marking to identify the technology options in spintronics, tunnel junction and photonics devices.[12][13][14]

He is also the founding editor-in-chief of IEEE Journal of Exploratory Solid State Computational Devices.

Awards and honours[edit]

  • 1992–2005: member of technical program committee of International Solid-State Circuits Conference (ISSCC)
  • 1994: December guest editor for the IEEE Journal of Solid-State Circuits (JSSCC)[15]
  • 1996: Fellow of Intel (highest technical position at Intel until 2002)[16]
  • 1996: April guest editor for JSSCC[15]
  • 1997: April guest editor for JSSCC[15]
  • 1999: Fellow of IEEE[17]
  • 1991–1996: program committee for the Symposium on VLSI Circuits[15]
  • 1995–1996: Chair of the technical program committee for the Symposium on VLSI Circuits
  • 1997–1998: chairman of the Symposium on VLSI Circuits[15]
  • 1997–2003: Digital Subcommittee chair of International Solid-State Circuits Conference (ISSCC)
  • 2004: Senior Fellow of Intel (highest technical position at Intel since 2002)[16]
  • 2005: Technical Program Committee chairman of the 2005 ISSCC
  • 2006–2011: member of administration committee of IEEE Solid-State Circuits Society
  • 2008–2010: IEEE Solid State Circuits Society, Distinguished Lecturer
  • 2009: International Solid-State Circuits Conference's Jack Raper Award for Outstanding Technology Directions paper[18]
  • 2012: Plenary Speaker at IEEE Device Research Conference
  • 2013: Guest Editor of IEEE Journal of Selected Topics in Quantum Electronics (JSTQE)
  • 2014: Editor-in-Chief of IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Selected works[edit]

  • Young, I.A.; Greason, J.K.; Wong, K.L.. "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors," Solid-State Circuits, IEEE Journal of, vol.27, no.11, pp. 1599–1607, Nov. 1992.[19]
  • Young, Ian A., Monte F. Mar, and Bharat Bhushan. "A 0.35 μm CMOS 3–880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors." Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC, 1997 IEEE International. IEEE, 1997.[20]
  • Young, I.A.; Hodges, D.A. "MOS switched-capacitor analog sampled-data direct-form recursive filters," IEEE Journal of Solid-State Circuits, vol.14, no.6, pp. 1020–1033, Dec. 1979[21]
  • Young, Ian. A History of the Continuously Innovative Analog Integrated Circuit.[22]
  • Young, Ian A., et al. "Optical I/O technology for tera-scale computing." Solid-State Circuits, IEEE Journal of 45.1 (2010): 235–248.[23]
  • Muthali, H.S.; Thomas, T.P.; Young, I.A. "A CMOS 10-gb/s SONET transceiver," Solid-State Circuits, IEEE Journal of, vol.39, no.7, pp. 1026– 1033, July 2004.[24]
  • Manipatruni, S.; Lipson, M.; Young, I. "Device Scaling Considerations for Nanophotonic CMOS Global Interconnects," IEEE Journal of Selected Topics in Quantum Electronics, vol.PP, no.99, pp. 1.[25]
  • D.E. Nikonov, I. A. Young, Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking IEDM 2012[12]
  • Avci, U.E.; Rios, R.; Kuhn, K.; Young, I.A. "Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic," VLSI Technology (VLSIT), 2011 Symposium on, vol., no., pp. 124,125, 14–16 June 2011.[26]
  • Manipatruni, S.; Nikonov. D.E.; Young, Ian."Material Targets for Scaling All-Spin Logic", Phys. Rev. Applied 5, 014002.[27]

Selected patents[edit]

  • 5,412,349, PLL clock generator integrated with microprocessor, 5 February 1995
  • 5,446,867, Microprocessor PLL clock circuit with selectable delayed feedback, 29 August 1995
  • 5,280,605, Clock speed limiter for microprocessor, 18 January 1994
  • 6,081,141, Hierarchical Clock Frequency Domains for a Semiconductor Device, 27 June 2000
  • 6,512,861, Packaging and assembly method for optical coupling, 28 January 2003
  • 6,636,976, Mechanism to Control di/dt for a Microprocessor, 21 October 2003
  • 6,075,908 Paniccia, Mario J., Valluri RM Rao, and Ian A. Young. "Method and apparatus for optically modulating light through the back side of an integrated circuit die." 13 June 2000.
  • 7,049,704 Chakravorty, K. K., Swan, J., Barnett, B. C., Ahadian, J. F., Thomas, T. P., & Young, I. (2006). US Patent No.
  • 6,125,217 Paniccia, M. J., Young, I. A., Thomas, T. P., & Rao, V. R. (2000)

References[edit]

  1. ^ "Intel Leadership Website". Newsroom.intel.com. Retrieved 27 February 2013.
  2. ^ Young, I.A.; Greason, J.K.; Wong, K.L. (November 1992). "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors". IEEE Journal of Solid-State Circuits. 27 (11): 1599–1607. doi:10.1109/4.165341.
  3. ^ [1]
  4. ^ [2]
  5. ^ "List of peer reviewed papers". Google Scholar. 15 February 2005. Retrieved 27 February 2013.
  6. ^ "List of Patents". Google. Retrieved 27 February 2013.
  7. ^ a b Young, I. A. MOS switched-capacitor analog sampled-data recursive filters (Thesis). University of California, Berkeley. p. 27. Bibcode:1978PhDT........27Y.
  8. ^ Young, I.A.; Hodges, D.A. (December 1979). "MOS switched-capacitor analog sampled-data direct-form recursive filters". IEEE Journal of Solid-State Circuits. 14 (6): 1020–1033. doi:10.1109/JSSC.1979.1051311.
  9. ^ Webb, C; Creek, R; Holt, W; King, G; Young, I (1986). "A 65 ns CMOS 1Mb DRAM". 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. p. 262. doi:10.1109/ISSCC.1986.1156984.
  10. ^ "first military certified very high speed IC, pp 76". Retrieved 27 February 2013.
  11. ^ Bohr, M.T (1995). "Interconnect scaling-the real limiter to high performance ULSI". Proceedings of International Electron Devices Meeting. p. 241. doi:10.1109/IEDM.1995.499187. ISBN 0-7803-2700-4.
  12. ^ a b Nikonov; Young (1 February 2013). "Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking". arXiv:1302.0244 [cond-mat.mes-hall].
  13. ^ Manipatruni, S.; Lipson, M.; Young, I. A. (March 2013). "Device Scaling Considerations for Nanophotonic CMOS Global Interconnects". IEEE Journal of Selected Topics in Quantum Electronics. 19 (2): 8200109–8200109. doi:10.1109/JSTQE.2013.2239262.
  14. ^ Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A. (December 2012). "Modeling and Design of Spintronic Integrated Circuits". IEEE Transactions on Circuits and Systems I: Regular Papers. 59 (12): 2801–2814. doi:10.1109/TCSI.2012.2206465.
  15. ^ a b c d e "IEEE Society News". Ieeexplore.ieee.org. Retrieved 27 February 2013.
  16. ^ a b "Intel Appoints New Fellows". Embedded. Retrieved 27 February 2013.
  17. ^ "Fellows: Y". IEEE. Retrieved 27 February 2013.
  18. ^ "About: 2009 Conference Awards". ISSCC. Retrieved 27 February 2013.
  19. ^ http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=165341&isnumber=4254
  20. ^ http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=585406
  21. ^ "IEEE Xplore – MOS switched-capacitor analog sampled-data direct-form recursive filters". Ieeexplore.ieee.org. 27 September 2011. doi:10.1109/JSSC.1979.1051311. Retrieved 27 February 2013.
  22. ^ "A History of the Continuously Innovative Analog Integrated Circuit". Ieee.org. Retrieved 27 February 2013.
  23. ^ "IEEE Xplore – Optical I/O Technology for Tera-Scale Computing". Ieeexplore.ieee.org. 27 September 2011. doi:10.1109/JSSC.2009.2034444. Retrieved 27 February 2013.
  24. ^ "IEEE Xplore – A CMOS 10-gb/s SONET transceiver". Ieeexplore.ieee.org. 27 September 2011. doi:10.1109/JSSC.2004.829935. Retrieved 27 February 2013.
  25. ^ "IEEE Xplore – Device Scaling Considerations for Nanophotonic CMOS Global Interconnects". Ieeexplore.ieee.org. 27 September 2011. doi:10.1109/JSTQE.2013.2239262. Retrieved 27 February 2013.
  26. ^ [3]
  27. ^ ["http://journals.aps.org/prapplied/abstract/10.1103/PhysRevApplied.5.014002]