Intel 4004

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Intel 4004
Intel C4004.jpg
White ceramic Intel C4004 microprocessor with grey traces
General information
LaunchedNovember 15, 1971; 50 years ago (November 15, 1971)
Discontinued1981
Common manufacturer(s)
  • Intel
Performance
Max. CPU clock rate740-750 kHz
Data width4 bits
Address width12 bits (multiplexed)
Architecture and classification
ApplicationBusicom calculator, arithmetic manipulation
Technology node10 μm
Instruction set4-bit BCD oriented
Physical specifications
Transistors
  • 2,300
Package(s)
Socket(s)
History
SuccessorIntel 4040

The Intel 4004 is a 4-bit central processing unit (CPU) released by Intel Corporation in 1971. Sold for US$60,[1] it was the first commercially produced microprocessor,[2] and the first in a long line of Intel CPUs.

The design traces its history to 1969, when Busicom Corp. approached Intel to design a controller for an electronic calculator. The complexity of the seven-chip design led Marcian Hoff to propose a single general-purpose chip instead. Design began in April 1970 under the direction of Federico Faggin aided by Masatoshi Shima who contributed to the architecture and later to the logic design. The first delivery of a fully operational 4004 was in March 1971 to Busicom for its 141-PF printing calculator engineering prototype (now displayed in the Computer History Museum in Mountain View, California).[3] General sales began July 1971.

A number of new techniques developed by Faggin while working at Fairchild Semiconductor allowed the 4004 to be produced on a single chip. The main concept was the use of the self-aligned gate process, where the circuitry on the chip connecting the various components was made of polysilicon rather than metal, which allowed the components to be much closer together. To make this work, Faggin had also developed the "bootstrap load" concept that reduced power requirements, and the "buried contact" that allowed the circuity to be connected directly to the individual transistors. These techniques had been pioneered on the Fairchild 3708 in 1968. Together, they doubled the circuit density, and thus halved cost, allowing a single chip to contain 2300 gates while running five times as fast as previous designs using metal interconnects.

The design was later updated as the Intel 4040 in 1974. The Intel 8008 and 8080 were unrelated designs in spite of the similar naming.

History[edit]

Original concept[edit]

In April 1969, Busicom approached Intel to produce a new design for an electronic calculator. They based their design on the architecture of the 1965 Olivetti Programma 101, one of the world's first tabletop programmable calculators.[4][5] The key difference was that the Busicom design would use integrated circuits to replace the printed circuit boards filled with individual components, and solid-state shift registers for memory instead of the costly magnetostriction wire in the 101.

In contrast to earlier calculator designs, Busicom had developed a general-purpose processor concept with the goal of introducing it in a low-end desktop printing calculator, and then using the same design for other roles like cash registers and automatic teller machines. The company had already produced a calculator using TTL small scale integration logic ICs and were interested in having Intel reduce the chip count using Intel's medium scale integration (MSI) techniques.[6]

Intel assigned the recently hired Marcian Hoff, employee number 12, to act as the liaison between the two companies. In late June, three engineers from Busicom travelled to Intel to introduce the design, Masatoshi Shima and his colleagues Masuda and Takayama. Although he had only been assigned to liaise with the engineers, Hoff began studying the concept. Their initial proposal had seven ICs, program control, arithmetic unit (ALU), timing, program ROM, shift registers for temporary memory, printer controller and input/output control.[7]

Hoff became concerned that the number of chips and the required interconnections between them would make Busicom's price goals impossible to meet. Combining the chips would reduce the complexity and cost. He was also concerned that the still-small Intel would not have enough design staff to make seven separate chips at the same time. He raised these concerns with upper management, and Bob Noyce, the CEO, told Hoff he would support a different approach if it seemed feasible.[7]

Simplified design[edit]

A key concept in the Busicom design was that the program control and ALU were not aimed specifically at the calculator market, it was the program in ROM that turned it into a calculator. The original idea was that the company could use the same chips with different amounts of shift register RAM and program ROM to produce a range of devices. Hoff was struck by how closely the resulting instruction set architecture matched that of general-purpose computers. He began to consider whether a truly general-purpose processor could be made cheaply enough to be used in a calculator.[8] When later asked where he got the ideas for the architecture of the first microprocessor, Hoff related that Plessey, "a British tractor company",[9] had donated a minicomputer to Stanford, and he had "played with it some" while he was there. Tadashi Sasaki attributes the idea to break the calculator into four parts to an unnamed woman from the Nara Women's College present at a brainstorming meeting that was held in Japan prior to his first meeting with Intel.[10]

Another development that allowed this design to be made practical was Intel's work on the earliest dynamic RAM (DRAM) chips. Shift registers were among the only low-cost memory devices of the era. They do not allow random access, instead, with every clock pulse they move the stored data one cell along a chain of cells. The time to retrieve any given data, one byte for instance, is a function of the clock speed and the number of cells in a chain. If the processor had to wait for each bit to cycle through the register the resulting effective speed would be far too low to be practical. DRAM, on the other hand, allowed random access to any data they stored, while also having roughly double the capacity and thus being less expensive.[8]

Finally, Hoff noticed that much of the complexity of the program control chip was due to every instruction being implemented separately. He suggested that the chip instead support subroutine calls and instructions be implemented as subroutes where possible. The concept naturally suggested a 4-bit design, as this allowed direct manipulation of binary coded decimal (BCD) values used by the calculator. Hoff worked on the overall design concept through July and August 1969 but found the Busicom executives seemed uninterested in the proposal.[8]

Mazor joins[edit]

Unknown to Hoff, the Busicom team were extremely interested in his proposal. However, there were a number of specific issues that they were concerned about. One key issue was that certain routines like decimal adjust and keyboard handling would use large amounts of ROM space if implemented as subroutines. Another was that the design did not feature any sort interrupt controller so dealing with events would be difficult. Finally, storing the numbers as 4-bit BCD would require additional memory to store the sign and decimal place.[11]

In September 1969, Stanley Mazor joined Intel from Fairchild. Hoff and Mazor quickly came up with solutions to the Busicom concerns. To address the complexity of the subroutines, originally solved in Busicom's design using one byte macroinstructions and complex decoder circuitry, Mazor developed a 20-byte long interpreter that executed the same macroinstructions. Shima suggested adding a new interrupt that would be triggered by a pin, thereby allowing the keyboard to be interrupt driven. He also modified the Branch Back (return from subroutine) instruction to clear the accumulator.[12]

To reach the price goals, it was important that the chip be as small as possible and use the fewest number of leads. As data was 4-bits and the address space was 12-bits (4096 bytes), there was no way direct access could be arranged with anything fewer than about 24-pins. This was not small enough, so the design would use a 16-pin dual in-line package (DIP) layout and use multiplexing of a single set of 4 lines. This meant specifying which address in ROM to access required three clock cycles, and another two to read it from memory. Running at 1 MHz would allow it to perform math on the BCD values at about 80 microseconds per digit.[13]

The resulting design was presented to a visiting team of Busicom executives in October 1969. They agreed the new concept was superior, and gave the company the go-ahead to begin production. Hoff was upset to learn that the contract assigned all rights to the design to Busicom, in spite of it being designed entirely within Intel. The team then left for Japan, but Shima remained in California until December, developing many of the subroutines.[13]

Faggin joins[edit]

Neither Hoff nor Mazar had experience designing the actual silicon, which was the purpose of Intel's Applications Research division. The group was already overworked with the memory devices being developed. In April 1970, Leslie Vadász, who ran the group, hired Federico Faggin from Fairchild Semiconductor to take over the design.[14] Faggin had already made a name for himself by introducing a new technique that was rapidly changing the entire semiconductor market.

Integrated circuits consist of a number of individual components like transistors and resistors that are produced by mixing the underlying silicon with "dopants". This is normally accomplished by heating the chip in the presence of a chemical gas, which diffuses into the surface. Previously, the individual components were connected together to make a circuit using aluminium wires deposited on the surface. As aluminum melts at 600 degrees and silicon at 1000, the traces typically had to be deposited as the last step, which often complicated the production cycle.

In 1967, Bell Labs released a paper on a new concept that used the silicon itself to form the wiring instead of a separate aluminum layer. Faggin and Tom Klein had taken what was a curiosity and developed the practical steps needed to use this in an IC, producing the Fairchild 3708[15] that was featured on the cover of Electronics (29 September 1969).[16] in 1968.[14] This technique meant the interconnections could be performed at any time in the process. More importantly, the wiring was deposited using the same equipment that made the rest of the components. This meant that the slight differences in layout between different machine types was eliminated. Previously the interconnects had to be much larger than required in order to ensure the aluminum touched the silicon components which would be offset due to inaccuracies in the machinery. With this issue eliminated, the circuits could be placed much closer together, immediately doubling the density of the components, and thus reducing their cost by the same amount. Additionally, the aluminum wiring acted as capacitors which limited the signal speed; removing these allowed the chips to run at faster speeds.[17][18]

At Intel, Faggin began design of the new processor using this self-aligned gate process. Only days after Faggin joined the company, Shima arrived and was disappointed to learn that no work on the project had taken place since he left in December, and expressed his concern the timeline was now impossible. Faggin responded by working well into the night every day, and Shima stayed on for another six months to help. Additional advances were needed to reach the required circuit density. One of these advances was the use of "buried contacts" that allowed the silicon connecting wires to be directly connected to the components,[19][20] another was adding "bootstrap loads" as part of one of the masking steps,[21] eliminating one step from the processing.[14]

Into production[edit]

The Unicom 141P is an OEM version of the Busicom 141-PF.

The result was a four-chip design. Intel's naming scheme of the era used a four-digit number for each component. The first digit indicated the process technology used, the second digit indicated the generic function, and the last two digits of the number were used to indicate the sequential number in the development of the component. Using this system, the chips would have been known as the 1302, 1105, 1507, and 1202. Faggin felt this would obscure the fact that they were designed as a group, and decided to name them as the "4000 family".[22] The four chips were the 4001 256-byte 4-bit ROM, the 4002 DRAM storing four 20-nibble digits, the 4003 serial-to-parallel converter for I/O, and the 4004 CPU. A fully expanded system could support 16 4001's for a total of 4 kB of ROM, 16 4002's for 1,280 nibbles (5 kB) of RAM, and up to 32 4003's. The 4003's were connected to pins on the 4001 and 4002, not directly to the CPU.[7]

With the design complete, Shima returned to Japan to begin building a prototype of the calculator. The first wafers of the 4001 were processed in October 1970,[14] followed by the 4003 and 4002 in November. The 4002 proved to have a minor problem that was corrected. The first 4004s arrived at the end of December, and found to be completely dead. Probing the chip, he found that one of the steps in the process had been left out. A second run with the missing process added was available in January 1971. Further testing found two minor problems, and the final design was produced in March.[23]

Faggin was sending samples of these chips to Shima as they arrived. In April, they learned the calculator prototype was operational. Later that month, Shima sent Intel the final masks for the 4001 ROMs, the design was now complete. It consisted of one 4004, two 4002, three 4003, and four 4001 chips. An additional 4001 supplied the optional square root function. One final change was added after Faggin found a frustrating problem in the 4001 that only occurred when the chips were hot, a new decoder circuit was added to address this, and also to the 4002 when the same effect was seen there. Production began in quantity in August 1971.[23]

Marketting the 4004[edit]

During a call to Shima, Faggin learned that Busicom was in financial difficulty and would likely fail if the chip set was not less expensive. Faggin and Hoff then convinced Noyce to lower the price for Busicom in exchange for releasing Intel from the exclusivity agreement. In May 1971 Busicom agreed to this, on the condition that it not be used for any other calculator project and that Intel would repay their $60,000 development costs.[23] With this change of marketing focus name of the chip family name was changed to MSC-4, short for Micro Computer System, 4-bit.[22]

Intel management was skeptical that their sales team could explain the product to their customers. As Intel was now successful in the memory market, they were concerned the 4004 might confuse the market and were hesitant to advertise it.[23] Hoff and Mazor were also concerned that the design's limitations would make it less interesting to users who were accustomed to the new 16-bit minicomputers entering the market at that time.[24]

This all changed in the summer of 1971, when Ed Gelbach, formerly of Texas Instruments, took over the marketing department and immediately began plans to publicly announce the product.[24] This took place in the November 1971 when Intel ran ads "Announcing a new era of integrated electronics,"[25] first appearing in the 15 November edition of Electronic News.[26]

The 8008[edit]

The 4004 came to market as the first microprocessor available for general purchase.[a] This was almost not the case.[24]

In December 1969, Intel was approached by Computer Terminal Corporation (CTC) to help them design a new memory device for a computer terminal they were designing, the Datapoint 2200. Mazor and Hoff considered their design and concluded it was not much more complicated than the 4004, and that it could be implemented as a single-chip 8-bit design.[13] A few weeks before they hired Faggin, in March 1970 Intel hired Hal Feeney to design, at that time using Intel's original naming, the 1201. However, CTC ran into financial difficulties and the project was lowered in priority. Feeney was assigned to other projects and ultimately ended up working under Faggin.[27]

In January 1971, Feeney was reassigned back to the 1201. Based on their experience gained during the 4004, this was a much quicker process and the first production chips were produced in March 1972. In May, Hoff and Mazor went on a speaking tour to introduce the two designs around the USA. The tradeoffs between the two designs were that the 4004 was somewhat faster and much easier to build a complete machine out of, while the 8008 could store code in ROM or RAM, had a larger 16 kB address space, and offered more instructions. A significant difference is that while a minimal 4004 system could be built using only two chips, the 4004 and a 4001, the 8008 would require about 20 additional TTL components for interfacing.[27]

The two designs found themselves being used in different roles. The 4004 was used where cost of implementation was the major concern, and became widely used in embedded controllers for things like microwave ovens and similar roles. The 8008 instead found itself mostly used in computer terminals, microcomputers and similar roles. This split in functionality remains to this day, with the former being known as a microcontroller.[27]

Contemporaneous CPU chips[edit]

Three other CPU chip designs were produced at about the same time: the Four-Phase Systems AL1, done in 1969; the MP944, completed in 1970 and used in the F-14 Tomcat fighter jet; and the Texas Instruments TMS-0100 chip, announced on 17 September 1971. The MP944 was a collection of six chips forming a single processor unit. The TMS0100 chip was presented as a "calculator on a chip" with the original designation TMS1802NC.[28] This chip contains a very primitive CPU and can only be used to implement various simple four-function calculators. It is the precursor of the TMS1000, introduced in 1974, which is considered the first microcontroller—i.e., a computer on a chip containing not only the CPU, but also ROM, RAM, and I/O functions.[29] The MCS-4 family of four chips developed by Intel, of which the 4004 is the CPU or microprocessor, was far more versatile and powerful than the single-chip TMS1000, allowing the creation of a variety of small computers for various applications.[citation needed]

Zilog, the first company entirely dedicated to microprocessors and microcontrollers, was started by Federico Faggin and Ralph Ungermann at the end of 1974.[30][31]

Description[edit]

National Semiconductor was a second-source manufacturer of the 4004, under their part number INS4004.[32]

The 4004 employs a 10 μm process silicon-gate enhancement-load pMOS technology on a 12 mm2 die[33] and can execute approximately 92000 instructions per second; a single instruction cycle is 10.8 microseconds.[34] The original clock rate design goal was 1 MHz, the same as the IBM 1620 Model I.[citation needed]

The Intel 4004 was designed by physically cutting sheets of Rubylith into thin strips to lay out the circuits to be printed, a process made obsolete by current computer graphic design capabilities.[35]

For the purpose of testing the produced chips, Faggin developed a tester for silicon wafers of MCS-4 family that was itself driven by 4004 chip. The tester also served as a proof for the management that Intel 4004 microprocessor could be used not only in calculator-like products, but also for control applications.[36]

The 4004 includes functions for direct low-level control of memory-chip selection and I/O, which are not normally handled by the microprocessor; however, its functionality is limited in that it cannot execute code from RAM and is limited to whatever instructions are provided in ROM (or an independently loaded RAM working as ROM—in either case, the processor is itself unable to write or transfer data into an executable memory space). The RAM and ROM parts were also unusual in their integration of output (and, in the ROMs, input) ports that significantly reduced the minimum part count in an MCS-4 system, but required inclusion of a certain amount of processor-like logic on the chips themselves to accept, decode and execute relatively high-level data-transfer instructions.

The standard arrangement for a 4004 system is anything up to 16 × 4001 ROM chips (in a single bank) and 16 × 4002 RAM chips (in four banks of four), which together provide the 4 KB program storage, 1024 + 256 nibbles of data/status storage, plus 64 output and 64 input/output external data/control lines (which can themselves be used to operate, e.g. a 4003). Intel's MCS-4 documentation, however, claims that up to 48 ROM and RAM chips (providing up to 192 external control lines) "in any combination" can be connected to the 4004 "with simple gating hardware", but declines to give any further detail or examples of how this would actually be achieved.

Technical specifications[edit]

Two C4004 DIPs, with one opened to show the die
Intel 4004 architectural block diagram
Intel 4004 DIP chip pinout
Intel 4004 registers
11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Accumulator
    A Accumulator
Condition codes
  C Carry flag
Index registers
  R0 R1  
  R2 R3  
  R4 R5  
  R6 R7  
  R8 R9  
  R10 R11  
  R12 R13  
  R14 R15  
Program counter
PC Program Counter
Push-down address call stack
PC1 Call level 1
PC2 Call level 2
PC3 Call level 3
  • Maximum clock rate is 740 kHz. The 4004 had this maximum clock rating upon its initial 1971 release.[b]
  • Instruction cycle time: minimum 10.8 μs[34] (8 clock cycles per machine cycle).
  • Instruction execution time 1 or 2 machine cycles (10.8 or 21.6 μs), 46250 to 92500 instructions per second.
    • Adding two 8-digit decimal numbers (32 bits each, assuming 4-bit BCD digits) takes a claimed 850 μs, or approximately 79 machine cycles (632 clock ticks), for an average of just under 10 cycles (80 ticks) per digit pair and an operating speed of 1176 × 8-digit additions per second[c]
  • Separate program and data storage. Contrary to Harvard architecture designs, however, which use separate buses, the 4004, with its need to keep pin count down, uses a single multiplexed 4-bit bus for transferring:
    • 12-bit addresses,
    • 8-bit instructions,
    • 4-bit data words.
  • Able to directly address 5120 bits (equivalent to 640 bytes) of RAM, stored as 1280 4-bit "characters" and organised into groups representing 1024 "data" and 256 "status" characters (512 and 128 bytes).[d]
  • Able to directly address 32768 bits of ROM, equivalent to and arranged as 4096 8-bit words (i.e. bytes).[e]
  • Instruction set contained 46 instructions (of which 41 were 8 bits wide and 5 were 16 bits wide).
  • Register set contains 16 registers of 4 bits each.
  • Internal subroutine stack, 3 levels deep.

Logic levels[edit]

Symbol Min. Max
VSS–DD +15 V − 5% +15 V + 5%
VIL VDD VSS − 5.5 V
VIH VSS − 1.5 V VSS + 0.3 V
VOL VSS − 12 V VSS − 6.5 V
VOH VSS − 0.5 V VSS

Support chips[edit]

  • 4001: 256-byte ROM (256 8-bit program instructions) and one built-in 4-bit I/O port. A 4001 ROM+I/O chip cannot be used in a system along with a 4008/4009 pair.[37]
  • 4002: 40-byte RAM (80 4-bit data words) and one built-in 4-bit output port; the RAM portion of the chip is organized into 4 "registers" of 20 4-bit words:
    • 16 data words (used for mantissa digits in the original calculator design), accessed in a relatively standard manner,
    • 4 status words (used for exponent digits and signs in the original calculator design), accessed using I/O type commands in place of the ROM's input channel.
  • 4003: 10-bit parallel output shift register for scanning keyboards, displays, printers, etc.
  • 4008: 8-bit address latch for access to standard memory chips and one built-in 4-bit chip-select and I/O port.
  • 4009: program and I/O access converter to standard memory and I/O chips.
  • 4269: keyboard/display interface.
  • 4289: memory interface (combined functions of 4008 and 4009).

The minimum system specification described by Intel consists of a 4004 with a single 256-byte 4001 program ROM; there is no explicit need for separate RAM in minimal-complexity applications thanks to the 4004's large number of onboard index registers, which represent the equivalent of 16 × 4-bit or 8 × 8-bit characters (or a mixture) of working RAM, nor for simple interface chips thanks to the ROM's built-in I/O lines. However, as project complexity increases, the various other support chips start to become useful.

Packaging[edit]

Numerous versions of the Intel MCS-4 line of processors were produced. The earliest versions, marked C (like C4004), were ceramic and used a zebra pattern of white and gray on the back of the chips, often called "grey traces". The next generation of the chips was plain white ceramic (also marked C), and then dark grey ceramic (D). Many of the more recent versions of MCS-4 family were also produced with plastic (P).

Use[edit]

The first commercial product to use a microprocessor was the Busicom calculator 141-PF. The 4004 was also used in the first microprocessor-controlled pinball game, a prototype produced by Dave Nutting Associates for Bally in 1974.

In 1996, The US Patent Office officially recognized Mr. Gary W. Boone and his employer, Texas Instruments, as the inventors of the single-chip microcontroller, overturning the patent grant to Gilbert P. Hyatt in 1990. Even though the patent had expired, it was thought to have potential financial impact depending on the details of previous contracts with Gilbert Hyatt.[38] According to Nick Tredennick, a microprocessor designer and expert witness to that Boone/Hyatt patent case:

Here are my opinions from [the] study [I conducted for the patent case]. The first microprocessor in a commercial product was the Four Phase Systems AL1. The first commercially available (sold as a component) microprocessor was the 4004 from Intel.[39]

A popular myth has it that Pioneer 10, the first spacecraft to leave the solar system, used an Intel 4004 microprocessor. According to Dr. Larry Lasher of Ames Research Center, the Pioneer team did evaluate the 4004, but decided it was too new at the time to include in any of the Pioneer projects.[citation needed] The myth was repeated by Federico Faggin himself in a lecture for the Computer History Museum in 2006.[40]

Legacy and value[edit]

In the lower-right corner of the CPU are the initials "F.F."

Federico Faggin signed the 4004 with his initials because he knew that his silicon gate design embodied "the essence of the microprocessor". A corner of the die reads "F.F."[22]

On 15 November 2006, the 35th anniversary of the 4004, Intel celebrated by releasing the chip's schematics, mask works, and user manual.[41] A fully functional 41 × 58 cm,[42] 130× scale replica of the Intel 4004 was built using discrete transistors and put on display in 2006 at the Intel Museum in Santa Clara, California.[43]

On 15 October 2010, Faggin, Hoff, and Mazor were awarded the National Medal of Technology and Innovation by President Barack Obama for their pioneering work on the 4004.[44]

See also[edit]

Notes[edit]

  1. ^ Several microprocessors had been designed or built by this point, but were not available for purchase outside the products they were part of.
  2. ^ Although the early documentation states "0.75 MHz", this is at odds with the timing diagrams, which specify a minimum overall cycle time of 1350 ns (=741 kHz) and a maximum of 2010 ns (=498 kHz).
  3. ^ This statistic comes from the same document as the "0.75 MHz" claim and which appears to inaccurately round off the true figures for the purposes of summary. 850 μs with a minimum 10.8 μs cycle time would in truth be 78.7 machine cycles, or roughly 629 clock ticks. As the processor is locked into an 8-tick cycle, it is more likely that this operation would take 79 or even 80 full cycles, thus 632 to 640 ticks and 853 to 864 μs (or 854 to 865 μs at a true 740 kHz), and reducing the actual execution speed to 1157–1172 (or 1156–1171) 8-digit additions per second.
  4. ^ However, this could only be used as working / data memory, and was non-executable: program code could not be stored in or run from RAM, as the processor kept the two memory areas strictly segregated at the microcode level. Instruction fetching forced assertion of the ROM chip-select line (and deassertion of the RAM select lines), and the chip had no way to "write" data to anything other than an IO port whilst the ROM area was selected.
  5. ^ The only part of the 4004 memory space capable of storing executable code, though also usable for general-purpose storage.

References[edit]

  1. ^ "The 40th birthday of—maybe—the first microprocessor, the Intel 4004". 2011-11-15.
  2. ^ "The Story of the Intel 4004". Intel.
  3. ^ "The Intel 4004 Microprocessor and the Silicon Gate Technology: The Busicom Engineering Prototype". Intel4004.com.
  4. ^ "Olivetti Programma 101 Electronic Calculator". The Old Calculator Web Museum. technically, the machine was a programmable calculator, not a computer.
  5. ^ "2008/107/1 Computer, Programma 101, and documents (3), plastic / metal / paper / electronic components, hardware architect Pier Giorgio Perotto, designed by Mario Bellini, made by Olivetti, Italy, 1965–1971". www.powerhousemuseum.com. Retrieved 2016-03-20.
  6. ^ Faggin et al. 1996, p. 10.
  7. ^ a b c Faggin et al. 1996, p. 11.
  8. ^ a b c Faggin et al. 1996, p. 12.
  9. ^ Possibly he had confused the Plessey name with that of Massey Ferguson, makers of agricultural machinery.
  10. ^ Aspray, William (1994-05-25). "Oral-History: Tadashi Sasaki". Interview #211 for the Center for the History of Electrical Engineering. The Institute of Electrical and Electronics Engineers, Inc. Retrieved 2013-01-02.
  11. ^ Faggin et al. 1996, p. 13.
  12. ^ Faggin et al. 1996, p. 14.
  13. ^ a b c Faggin et al. 1996, p. 15.
  14. ^ a b c d Faggin et al. 1996, p. 16.
  15. ^ Faggin, Federico. "A faster generation of MOS devices with low thresholds is riding the crest of the new wave, silicon-gate IC's". Retrieved 2017-06-03.
  16. ^ Faggin, Federico. "Earliest Published Papers". Retrieved 2017-06-03.
  17. ^ Faggin, Federico. "The New Methodology for Random Logic Design". Retrieved 2017-06-03.
  18. ^ Federico Faggin, T. Klein (1970). "Silicon-Gate Technology". Solid State Electronics. Vol. 13. pp. 1125–1144
  19. ^ Faggin, Federico. "The Buried Contact". Retrieved 2017-06-03.
  20. ^ "Inductee Detail". National Inventors Hall of Fame. July 25, 2016.
  21. ^ Faggin, Federico. "The Bootstrap Load". Retrieved 2017-06-03.
  22. ^ a b c "Federico Faggin's Signature". Intel4004.com. Retrieved 2012-08-21.
  23. ^ a b c d Faggin et al. 1996, p. 17.
  24. ^ a b c Faggin et al. 1996, p. 18.
  25. ^ Cass, Stephen (2018-07-02). "Chip Hall of Fame: Intel 4004 Microprocessor". Retrieved 2019-02-05.
  26. ^ Gilder, George (1990). Microcosm: the quantum revolution in economics and technology. Simon and Schuster. p. 107. ISBN 978-0-671-70592-3. Intel's first advertisement for the 4004 appeared in the November 15, 1971 issue of Electronic News
  27. ^ a b c Faggin et al. 1996, p. 19.
  28. ^ Woerner, Joerg (2001-11-16). "The "Calculator-on-a-chip"". Datamath Calculator Museum. Retrieved 2016-03-22.
  29. ^ Woerner, Joerg (2001-02-26). "Texas Instruments: They invented the Microcontroller". Datamath Calculator Museum. Retrieved 2016-03-22.
  30. ^ "ZILOG Oral History Panel on the Founding of the Company and the development of the Z80 Microprocessor" (PDF).
  31. ^ "Ungerman-Bass in Brief".
  32. ^ Intel 4004 microprocessor family, retrieved 14 Dec 2011.
  33. ^ "History of Computing Industrial Era 1970–1971". 2010-10-19. Archived from the original on 2012-06-25. Retrieved 2016-05-05. In February Intel releases the 4004 microprocessor to the market. It has 12 sq mm die size and 16 pins which fit into a motherboard.
  34. ^ a b "Intel 4004 datasheet" (PDF) (published 2010-07-06). 1987. Archived from the original (PDF) on 2011-06-01. Retrieved 2020-12-18.
  35. ^ "Intel's Accidental Revolution". CNet.com. Archived from the original on 2012-07-11. Retrieved 2009-07-30.
  36. ^ Hendrie, Gardner (2006). "Oral History of Federico Faggin" (PDF). Computer History Museum. Archived from the original (PDF) on 2017-01-10. Retrieved 2017-01-24.
  37. ^ IMPORTANT section at page 25: http://www.intel.com/Assets/PDF/Manual/msc4.pdf.
  38. ^ John Markoff (1996-06-20). "For Texas Instruments, Some Bragging Rights". New York Times.
  39. ^ "Dissertation 2004" (PDF). Retrieved 2017-11-14.
  40. ^ "Intel 4004 Microprocessor 35th Anniversary". YouTube. Retrieved 2011-07-06.
  41. ^ Intel 4004 Microprocessor Historical Materials, Intel Museum, 2009-11-15, accessed 2009-11-18
  42. ^ "4004 @ 44: SVG Mask Artwork; New Busicom 141-PF replica PCB; Printer emulator". 2015-11-20. Retrieved 2016-05-05.
  43. ^ "Intel 4004 -- 45th Anniversary Project". 2015-11-15. Retrieved 2016-04-02. including fully functional 130x scale replicas of the 4004 built using discrete transistors, museum-durable keyboards and slide switches, and video display electronics.
  44. ^ "President Obama Honors Nation's Top Scientists and Innovators". whitehouse.gov (Press release). 2010-10-15 – via National Archives.

Sources[edit]

Patents[edit]

  • US 3753011  14 August 1973. Faggin, Federico: Power supply settable bi-stable circuit.
  • US 3821715  28 June 1974. Hoff, Marcian; Mazor, Stanley; Faggin, Federico: Memory system for multi-chip digital computer.

Historical documents[edit]

  • Faggin, Federico; Hoff Jr., Marcian; Mazor, Stanley; Shima, Masatoshi (December 1996). "The history of the 4004". IEEE Micro. Vol. 16, no. 6. pp. 10–20.
  • Faggin, Federico; Capocaccia, F. "A New Integrated MOS Shift Register", Proceedings XV International Electronics Scientific Congress, Rome, April 1968, pp. 143–152. This paper describes a novel static MOS shift register, developed at SGS-Fairchild (now ST Micro) at the end of 1967, before Federico Faggin joined Fairchild's R&D in Palo Alto (Ca) in February 1968. Faggin later used this new shift register in the MCS-4 chips, including the 4004.
  • Cover and abstract of the IEDM (International Electron Devices Meeting) Program (October 1968). The Silicon Gate Technology (SGT) was first presented by its developer, Federico Faggin, at the IEDM on 23 October 1968, in Washington, D.C. It was the only commercial process technology for the fabrication of MOS integrated circuits with self-aligned gate that was later universally adopted by the semiconductor industry. The SGT was the first technology to produce commercial dynamic RAMs, CCD image sensors, non volatile memories and the microprocessor, providing for the first time all the fundamental elements of a general purpose computer with LSI integrated circuits.
  • Cover of Electronics Magazine (29 September 1969). The Electronics article introduces the Fairchild 3708, designed by Federico Faggin in 1968. It was the world's first commercial integrated circuit using the Silicon Gate Technology, proving its viability.
  • Initials F.F. (Federico Faggin) on the 4004 design (1971). The 4004 bears the initials F.F. of its designer, Federico Faggin, etched on one corner of the chip. Signing the chip was a spontaneous gesture of proud authorship and was also an original idea imitated after him by many Intel designers.
  • Busicom 141-PF Printing Calculator Engineering Prototype (1971). (Gift of Federico Faggin to the Computer History Museum, Mountain View, CA). The CHM collection catalog shows pictures of the engineering prototype of the Busicom 141-PF desktop calculator. The engineering prototype used the world's first microprocessor to have ever been produced. This one-of-a-kind prototype was a personal present by Busicom's president Mr. Yoshio Kojima to Federico Faggin for his successful leadership of the design and development of the 4004 and three other memory and I/O chips (the MCS-4 chipset). After keeping it in his home for 25 years, Faggin donated it to the CHM in 1996.
  • Federico Faggin and M. E. Hoff: "Standard parts and custom design merge in four-chip processor kit". Electronics/24 April 1972, pp. 112–116. Reprinted on pp. 6–27 to 6–31 of The Intel Memory Design Handbook: August 1973.
  • Federico Faggin, M. Shima, M. E. Hoff, Jr., H. Feeney, S. Mazor: "The MCS-4—An LSI micro computer system". IEEE '72 Region Six Conference. Reprinted on pp. 6–32 to 6–37 of The Intel Memory Design Handbook: August 1973.

Further reading[edit]

External links[edit]