Intel 5-level paging

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A diagram of five levels of paging

Intel 5-level paging, referred to simply as 5-level paging in Intel documents, is a processor extension for the x86-64 line of processors.[1]:11 It extends the size of virtual addresses from 48 bits to 57 bits, increasing the addressable virtual memory from 256 TiB to 128 PiB. The extension was first implemented in the Ice Lake processors,[2] and the 4.14 Linux kernel adds support for it.[3]

Technology[edit]

x86-64 processors without this feature use a four-level page table structure when operating in 64-bit mode.[4]:2806 A similar situation arose when the 32 bit IA-32 processors used two levels, allowing up to four GiB of memory (both virtual and physical). To support more than 4 GB of RAM, an additional mode of address translation called Physical Address Extension (PAE) was defined, involving a third level.[5] This was enabled by setting a bit in the CR4 register.[4]:2799 Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57).[1]:16 This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.[1]:16 If the bit is not set, the processor operates with four paging levels.

As adding another page table multiplies the address space by 512, the virtual limit has increased from 256 TiB to 128 PiB. An extra nine bits of the virtual address index the new table, so while formerly bits 0 through 47 were in use, now bits 0 through 56 are in use.

As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five-level paging enabled, this means that bits 57 through 63 must be copies of bit 56.[1]:17 Intel has renamed the existing paging system as "4-level paging", which used to be known as IA-32e paging.[4]:2788

Extending page table entry to 128 bits allows full 64-bit address space in 4-level paging scheme, and makes possible arbitrary allocation unit sizes in 5-level scheme.[6]

Implementation[edit]

5-level paging is implemented by the Ice Lake microarchitecture.[2]

Support for the extension was submitted as a set of patches to the Linux kernel on 8 December 2016.[7] As was reported on the Linux kernel mailing list, it consisted of extending the Linux memory model to use five levels rather than four.[8] This is because, although Linux abstracts the details of the page tables, it still depends on having a number of levels in its own representation. When an architecture supports fewer levels, Linux emulates extra levels that do nothing.[9] A similar change was previously made to extend from three levels to four.[10]

Drawbacks[edit]

Adding another level of indirection makes page table "walks" longer.[11] A page table walk occurs when either the processor's memory management unit or the memory management code in the operating system navigates the tree of page tables to find the page table entry corresponding to a virtual address.[12][4]:2806 This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed.[13] In practice this cost is greatly mitigated by caches such as the translation lookaside buffer (TLB).[13] Further extensions may reduce page walks by using 4096 128-bit page table entries, and allow a larger 64 KiB page allocation size and backward compatibility with 4 KiB page operations. [6]

References[edit]

  1. ^ a b c d "5-Level Paging and 5-Level EPT" (PDF). Intel Corporation. May 2017.
  2. ^ a b Cutress, Ian. "Sunny Cove Microarchitecture: A Peek At the Back End". Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86. Retrieved 15 October 2019.
  3. ^ Tung, Liam. "First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday | ZDNet". ZDNet. Retrieved 25 April 2018.
  4. ^ a b c d Intel® 64 and IA-32 Architectures Software Developer's Manual (PDF). Intel Corporation. 2018.
  5. ^ Hudek, Ted. "Operating Systems and PAE Support - Windows 10 hardware dev". docs.microsoft.com. Retrieved 26 April 2018.
  6. ^ a b US patent 9858198, Larry Seiler, "64KB page system that supports 4KB page operation", published 2016-12-29, issued 2018-01-02, assigned to Intel Corp. 
  7. ^ Michael Larabel (9 December 2016). "Intel Working On 5-Level Paging To Increase Linux Virtual/Physical Address Space - Phoronix". Phoronix. Retrieved 26 April 2018.
  8. ^ Shutemov, Kirill A. (8 December 2016). "[RFC, PATCHv1 00/28] 5-level paging". Linux kernel mailing list (Mailing list). Retrieved 26 April 2018.
  9. ^ "Page Table Management". www.kernel.org. Retrieved 26 April 2018.
  10. ^ "Four-level page tables [LWN.net]". lwn.net. 12 October 2004. Retrieved 26 April 2018.
  11. ^ MICRO-50 : the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA. Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming. New York, New York. 14 October 2017. ISBN 9781450349529. OCLC 1032337814.CS1 maint: others (link)
  12. ^ "ARM Information Center". infocenter.arm.com. Retrieved 26 April 2018.
  13. ^ a b Levy, Hank (Autumn 2008). "CSE 451: Operating Systems: Paging & TLBs" (PDF). University of Washington. Retrieved 26 April 2018.