Intel 5-level paging

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A diagram of five levels of paging

Intel 5-level paging, referred to simply as 5-level paging in Intel documents, is a possible future processor extension for the x86-64 line of processors.[1]:11 It extends the size of virtual addresses from 48 bits to 57 bits, increasing the addressable virtual memory from 256 terabytes to 128 petabytes.[NB 1] While the technical document describing the extension is a white paper, stating "do not finalize a design with this information", support for the extension has already been implemented in the Linux kernel.[2]

Technology[edit]

Current x86-64 processors use a four-level page table structure when operating in 64-bit mode.[3]:2806 A similar situation arose when the 32 bit IA-32 processors used two levels, allowing up to four gigabytes of memory (both virtual and physical). To support more than 4 GB of RAM, an additional mode of address translation called Physical Address Extension (PAE) was defined, involving a third level.[4] This was enabled by setting a bit in the CR4 register.[3]:2799 Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57).[1]:16 This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.[1]:16 If the bit is not set, the processor operates with four paging levels.

The new extensions allow up to 4 PB of physical memory,[5] compared to the maximum of 256 TB on previous processors.[6] As adding another page table multiplies the address space by 512, the virtual limit has increased from 256 TB to 128 PB. An extra nine bits of the virtual address index the new table, so while formerly bits 0 through 47 were in use, now bits 0 through 56 are in use.

As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five-level paging enabled, this means that bits 57 through 63 must be copies of bit 56.[1]:17 Intel has renamed the existing paging system as "4-level paging", which used to be known as IA-32e paging.[3]:2788

Implementation[edit]

5-level paging is implemented by Ice Lake processors based on the Sunny Cove architecture.[7]

Support for the extension was submitted as a set of patches to the Linux kernel on 8 December 2016.[5] As was reported on the Linux kernel mailing list, it consisted of extending the Linux memory model to use five levels rather than four.[8] This is because, although Linux abstracts the details of the page tables, it still depends on having a number of levels in its own representation. When an architecture supports fewer levels, Linux emulates extra levels that do nothing.[9] A similar change was previously made to extend from three levels to four.[10]

Drawbacks[edit]

Adding another level of indirection makes page table "walks" longer.[11] A page table walk occurs when either the processor's memory management unit or the memory management code in the operating system navigates the tree of page tables to find the page table entry corresponding to a virtual address.[12][3]:2806 This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed.[13] In practice this cost is greatly mitigated by caches such as the translation lookaside buffer (TLB).[13]

Notes[edit]

  1. ^ Transistorized memory, such as RAM, ROM, flash and cache sizes as well as file sizes are specified using binary meanings for K (10241), M (10242), G (10243), ...

References[edit]

  1. ^ a b c d "5-Level Paging and 5-Level EPT" (PDF). Intel Corporation. May 2017.
  2. ^ Tung, Liam. "First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday | ZDNet". ZDNet. Retrieved 25 April 2018.
  3. ^ a b c d Intel® 64 and IA-32 Architectures Software Developer’s Manual (PDF). Intel Corporation. 2018.
  4. ^ Hudek, Ted. "Operating Systems and PAE Support - Windows 10 hardware dev". docs.microsoft.com. Retrieved 26 April 2018.
  5. ^ a b Michael Larabel (9 December 2016). "Intel Working On 5-Level Paging To Increase Linux Virtual/Physical Address Space - Phoronix". Phoronix. Retrieved 26 April 2018.
  6. ^ "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors" (PDF). p. 24. Retrieved 26 April 2018. Physical address space increased to 48 bits.
  7. ^ Cutress, Ian. "Sunny Cove Microarchitecture: A Peek At the Back End". Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86. Retrieved 15 October 2019.
  8. ^ Shutemov, Kirill A. (8 December 2016). "[RFC, PATCHv1 00/28] 5-level paging". Linux kernel mailing list (Mailing list). Retrieved 26 April 2018.
  9. ^ "Page Table Management". www.kernel.org. Retrieved 26 April 2018.
  10. ^ "Four-level page tables [LWN.net]". lwn.net. 12 October 2004. Retrieved 26 April 2018.
  11. ^ MICRO-50 : the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA. Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming,. New York, New York. ISBN 9781450349529. OCLC 1032337814.CS1 maint: extra punctuation (link) CS1 maint: others (link)
  12. ^ "ARM Information Center". infocenter.arm.com. Retrieved 26 April 2018.
  13. ^ a b Levy, Hank (Autumn 2008). "CSE 451: Operating Systems: Paging & TLBs" (PDF). University of Washington. Retrieved 26 April 2018.