||This article includes a list of references, but its sources remain unclear because it has insufficient inline citations. (October 2010)|
The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and counting functions. They were primarily designed for the Intel 8080/8085-processors, but later used in x86-systems. They (or an equivalent circuit embedded in a larger chip) are found in all IBM PC compatibles.
- 1 History
- 2 Features
- 3 Operation Modes
- 4 Programming Considerations
- 5 See also
- 6 References
- 7 Further reading
- 8 External links
The 8253 was used in IBM PC compatibles since their introduction in 1981. In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard's southbridge chipset. In some modern chipsets, this change may show up as measurable timing differences in accessing a PIT using the x86 I/O address space. Reads and writes to such a PIT's registers in the I/O address space may complete much faster.
Newer motherboards also include a counter through the Advanced Configuration and Power Interface (ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC), and a High Precision Event Timer. The CPU itself also provides the Time Stamp Counter (TSC) facility.
The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.
There are 3 counters (or timers), which are labeled as "Counter 0", "Counter 1" and "Counter 2". Each counter has 2 input pins – "CLK" (clock input) and "GATE" – and 1-pin, "OUT", for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU.
In the original IBM PCs, the first counter (selected by setting A1=A0=0, see Control Word Register below) is used to generate a timekeeping interrupt. The second counter (A1=0, A0=1) is used to trigger the refresh of DRAM memory. The last counter (A1=1, A0=0) is used to generate tones via the PC speaker.
Besides the counters, a typical Intel 8253 microchip also contains the following components:
This block contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the LSB.
The Read/Write Logic block has 5 pins, which are listed below. Notice that "/X" denotes an active low signal.
- /RD: read signal
- /WR: write signal
- /CS: chip select signal
- A0, A1: address lines
Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.
Control Word Register
Port 43h R/W
Port 53h R/W – second chip…
This register contains the programmed information which will be sent (by the microprocessor) to the device. It defines how the PIT logically works. Each access to these ports takes about 1 µs.
To initialize the counters, the microprocessor must write a control word (CW) in this register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data/Bus Buffer block.
The control word register contains 8 bits, labeled D7..D0 (D7 is the MSB).
|0||0||x||x||x||x||x||x||Counter 0 at port 40h R/W|
|0||1||x||x||x||x||x||x||Counter 1 at port 41h R/W|
|1||0||x||x||x||x||x||x||Counter 2 at port 42h R/W|
|x||x||0||0||x||x||x||x||Counter Latch, value can be read out in the way RW1, RW0 was set before. The value is held until it is read out or overwritten.|
|x||x||0||1||x||x||x||x||Read/Write bits 0..7 of counter value|
|x||x||1||0||x||x||x||x||Read/Write bits 8..15 of counter value|
|x||x||1||1||x||x||x||x||2xRead/2xWrite bits 0..7 then 8..15 of counter value|
|x||x||x||x||0||0||0||x||Mode 0: Interrupt on Terminal Count|
|x||x||x||x||0||0||1||x||Mode 1: Hardware Retriggerable One-Shot|
|x||x||x||x||0||1||0||x||Mode 2: Rate Generator|
|x||x||x||x||0||1||1||x||Mode 3: Square Wave|
|x||x||x||x||1||0||0||x||Mode 4: Software Triggered Strobe|
|x||x||x||x||1||0||1||x||Mode 5: Hardware Triggered Strobe (Retriggerable)|
|x||x||x||x||x||x||x||0||Counter is a 16 bit binary counter(0..65535,FFFFh)|
|x||x||x||x||x||x||x||1||Counter is a 16 bit decimal counter 4 x 4bit decades(0..9999)|
|1||1||0||1||x||x||x||0||Counter(C0..C2) value(s) can be read out.|
When setting the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising edge from the GATE input signal.
On PCs the address for timer0 (chip) is at port 40h..43h like described and the second timer1 (chip) is at 50h..53h.
The Status Byte is read like an 8 bit counter value (port 40h..42h R).
Bit# D7 D6 D5 D4 D3 D2 D1 D0 Name output null RW1 RW0 M2 M1 M0 BCD count ------------------------------------------- 0 x x x x x x x Out Pin is 0 1 x x x x x x x Out Pin is 1 ------------------------------------------- x 0 x x x x x x The value of the latch is loaded into the counter. A new value can be written to the latch. x 1 x x x x x x Counter value is 0. ------------------------------------------- x x = = = = = = like defined in the Control Word Register
The D3, D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to enable counting. For mode 5, the rising edge of GATE starts the count. For details on each mode, see the reference links.
Mode 0 (000): Interrupt on Terminal Count
Mode 0 is used for the generation of accurate time delay under software control. In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency.
The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The Gate signal should remain active high for normal counting. If Gate goes low counting gets terminated and current count is latched till Gate pulse goes high again. the first byte of the new count when loaded in the count register,stop the previous count.
Mode 1 (001): Programmable One Shot
In this mode 8253 can be used as Monostable Multivibrator. GATE input is used as trigger input.
OUT will be initially high. OUT will go low on the Clock pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.
The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
Mode 2 (X10): Rate Generator
In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt.
Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will then go high again, and the whole process repeats itself.
The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula:
Value to be loaded into counter =
Note that the values in the COUNT register range from to 1; the register never reaches zero.
Mode 3 (X11): Square Wave Generator
This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different from mode 2.
Suppose is the number loaded into the counter (the COUNT message), the output will be
- high for counts, and low for counts, if is even.
- high for counts, and low for counts, if is odd.
Mode 4 (100): Software Triggered Strobe
After Control Word and COUNT is loaded, the output will remain high until the counter reaches zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) – after that the output will become high again.
Mode 5 (101): Hardware Triggered Strobe
This mode is similar to mode 4. However, the counting process is triggered by the GATE input.
After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE.
On x86 PCs, many video card BIOS and system BIOS will reprogram the second counter for their own use. Reprogramming typically happens during video mode changes, when the video BIOS may be executed, and during system management mode and power saving state changes, when the system BIOS may be executed. This prevents any serious alternative uses of the timer's second counter on many x86 systems.
The timer that is used by the system on x86 PCs is Channel 0, and its clock ticks at a theoretical value of 1193181.8181... Hz, i.e. one third of the NTSC color subcarrier frequency, which comes from dividing the system clock (14.31818 MHz) by 12. This is a holdover of the very first CGA PCs – they derived all necessary frequencies from a single quartz crystal, and to make TV output possible, this quartz had to run at a multiple of the NTSC color subcarrier frequency.
As stated above, Channel 0 is implemented as a counter. Typically, the initial value of the counter is set by sending bytes to the Control, then Data I/O Port registers (the value 36h sent to port 43h, then the low byte to port 40h, and port 40h again for the high byte). The counter counts down to zero, then sends a hardware interrupt (IRQ 0, INT 8) to the CPU. The counter then resets to its initial value and begins to count down again. The fastest possible interrupt frequency is a little over a half of a megahertz. The slowest possible frequency, which is also the one normally used by computers running MS-DOS or compatible operating systems, is about 18.2 Hz. Under these real mode operating systems, the BIOS accumulates the number of INT 8 calls that it receives in real mode address 0040:006c, which can be read by a program.
As a timer counts down, its value can also be read directly by reading its I/O port twice, first for the low byte, and then for the high byte. However, in free-running counter applications such as in the x86 PC, it is necessary to first write a latch command for the desired channel to the control register, so that both bytes read will belong to one and the same value.
According to a 2002 Microsoft document, "because reads from and writes to this hardware  require communication through an IO port, programming it takes several cycles, which is prohibitively expensive for the OS. Because of this, the aperiodic functionality is not used in practice."
- "Guidelines For Providing Multimedia Timer Support". 20 September 2002. Retrieved 2010-10-13.
- "Intel 82c54 PIT Datasheet" (PDF).
- "8254/82C54: Introduction to Programmable Interval Timer". Intel Corporation. Retrieved 21 August 2011.
- "MSM 82c53 Datasheet" (PDF).
- Guidelines For Providing Multimedia Timer Support
- Gilluwe, Frank van. The Undocumented PC. A-W Developers Press, 1997. ISBN 0-201-47950-8