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Xeon Phi is a main/co processor designed, manufactured, marketed, and sold by Intel. It is primarily focused toward the supercomputer and enterprise markets (including servers, and workstations). When used in a supercomputer, server, or workstation environment it will usually work alongside an existing Intel Xeon processor or processor(s). Unlike Intel Core i7, Intel Xeon CPUs that are reliant on the LGA 2011-3 CPU socket, Xeon Phi CPUs require PCI Express v3 x16 in either x8 or x16 mode. The default in most cases is "auto switching".
The product falls into the Many Integrated Core (MIC) architecture and prototype products codenamed Knights Ferry were announced and released to developers in 2010. The Knights Corner product was announced in 2011 and uses a 22 nm process. A second generation product codenamed Knights Landing using a 14 nm process was announced in June 2013.
In November 2012, Intel formally announced the first products citing claims of CPU-like versatile programmability, high performance and power efficiency. The Green 500 list placed a system using these new products as the most power efficient computer in the world.
In June 2013, the Tianhe-2 supercomputer at the National Supercomputing Center in Guangzhou (NSCC-GZ) was announced as the world's fastest supercomputer. It utilizes Intel Xeon Phi coprocessors and Ivy Bridge-EP Xeon processors to achieve 33.86 petaFLOPS.
The Larrabee microarchitecture (in development since 2006) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing the Larrabee chips also included specialised hardware for texture sampling. The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010.
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single-chip Cloud Computer' (prototype introduced 2009), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for interchip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.
The Teraflops Research Chip (prototype unveiled 2007) is an experimental 80-core chip with two floating point units per core, implementing a 96-bit VLIW architecture instead of the x86 architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.
Intel's MIC prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced May 31, 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.
The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 KB per core with 32 KB L1 cache), and a power requirement of ~300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory. Single board performance has exceeded 750 GFLOPS. The prototype boards only support single precision floating point instructions.
Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.
In June 2011, SGI announced a partnership with Intel to utilize the MIC architecture in its high performance computing products. In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10 petaFLOPS "Stampede" supercomputer, providing 8 petaFLOPS of the compute power. According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."
On June 5, 2012, Intel released open source software and documentation regarding Knights Corner.
On June 18, 2012, Intel announced at the 2012 Hamburg International Supercomputing Conference that Xeon Phi will be the brand name used for all products based on their Many Integrated Core architecture. In June 2012, Cray announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems.
In June 2012, ScaleMP announced it will provide its virtualization software to allow using 'Knight's Corner' chips (branded as 'Xeon Phi') as main processor transparent extension. The virtualization software will allow 'Knight's Corner' to run legacy MMX/SSE code and access unlimited amount of (host) memory without need for code changes. An important component of the Intel Xeon Phi coprocessor’s core is its vector processing unit (VPU). The VPU features a novel 512-bit SIMD instruction set, officially known as Intel® Initial Many Core Instructions (Intel® IMCI). Thus, the VPU can execute 16 single-precision (SP) or 8 double-precision (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers. The VPU also features an Extended Math Unit (EMU) that can execute transcendental operations such as reciprocal, square root, and log, thereby allowing these operations to be executed in a vector fashion with high bandwidth. The EMU operates by calculating polynomial approximations of these functions
On November 12, 2012, Intel announced two Xeon Phi coprocessor families using the 22 nm process size: the Xeon Phi 3100 and the Xeon Phi 5110P. The Xeon Phi 3100 will be capable of more than 1 teraFLOPS of double precision floating point instructions with 240 GB/sec memory bandwidth at 300 W. The Xeon Phi 5110P will be capable of 1.01 teraFLOPS of double precision floating point instructions with 320 GB/sec memory bandwidth at 225 W. The Xeon Phi 7120P will be capable of 1.2 teraFLOPS of double precision floating point instructions with 352 GB/sec memory bandwidth at 300 W.
On June 17, 2013, the Tianhe-2 supercomputer was announced by TOP500 as the world's fastest. It used Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 petaFLOPS. According to the TOP500 list, Tianhe-2 was the world's fastest supercomputer since its introduction in June 2013 through the most recent list in November 2015.
Code name for the second generation MIC architecture product from Intel. Intel officially first revealed details of its second generation Intel Xeon Phi products on June 17, 2013. Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's 14nm process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth.
Knights Landing will be built using up to 72 Airmont (Atom) cores with four threads per core, supporting for up to 384 GB of "far" DDR4 RAM and 8–16 GB of stacked "near" 3D MCDRAM, a version of High Bandwidth Memory. Each core will have two 512-bit vector units and will support AVX-512 SIMD instructions, specifically the Intel AVX-512 Foundational Instructions (AVX-512F) with Intel AVX-512 Conflict Detection Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF).
The National Energy Research Scientific Computing Center announced that Phase 2 of its newest supercomputing system "Cori" would use Knights Landing Xeon Phi coprocessors.
On June 20, 2016, Intel launched the Intel Xeon Phi product family x200 based on the Knights Landing architecture, stressing its applicability to not just traditional simulation workloads, but also to machine learning. The model lineup announced at launch included only Xeon Phi of bootable form-factor, but two versions of it: standard processors and processors with integrated Intel Omni-Path architecture fabric. The latter is denoted by the suffix F in the model number. Integrated fabric is expected to provide better the latency lower cost than discrete high-performance network cards.
Knights Hill is the codename for the third-generation MIC architecture, for which Intel announced the first details at SC14. It will be manufactured in a 10 nm process.
In April 2015, the United States Department of Energy announced that a supercomputer named Aurora will be deployed at Argonne National Laboratory based upon the "third-generation Intel Xeon Phi" processor.
Knights Mill is Intel's codename for a Xeon Phi product specialized in deep learning. While little is known about Knights Mill yet, it has been announced that it will improve efficiency. It is also expected to support reduced variable precision which have been used to accelerate machine learning in other products, such as half-precision floating-point variables in Nvidia's Tesla.
The cores of Knights Corner are based on a modified version of P54C design, used in the original Pentium. The basis of the Intel MIC architecture is to leverage x86 legacy by creating a x86-compatible multiprocessor architecture that can utilize existing parallelization software tools. Programming tools include OpenMP, OpenCL, Cilk/Cilk Plus and specialised versions of Intel's Fortran, C++ and math libraries.
Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core), and ultra-wide ring bus connecting processors and memory.
An empirical performance and programmability study has been performed by researchers, in which the authors claim that achieving high performance with Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is still far from reality. However, research in various domains, such as life sciences, deep learning and computer-aided engineering demonstrated that exploiting both the thread- and SIMD-parallelism of Xeon Phi achieves significant speed-ups.
- Nvidia Tesla, a direct competitor in the HPC market
- AMD FireStream, another direct competitor in the HPC market
- Texas Advanced Computing Center - "Stampede" supercomputer incorporates Xeon Phi chips. Stampede is capable of 10 petaFLOPS.
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Intel(R) Xeon(R) Phi(TM) is the new brand name for all future Intel(R) Many Integrated Core Architecture based products targeted at HPC, enterprise, datacenters and workstations. The first Intel(R) Xeon(R) Phi(TM) product family member is scheduled for volume production by the end of 2012
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|Wikimedia Commons has media related to Intel MIC.|
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Today, with the announcement of Intel® Xeon® Phi™ coprocessors, we’re going to accelerate the pace of these discoveries and innovations. Intel® Xeon Phi products extend the Intel® Xeon® brand..
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