|Max. CPU clock rate||1.053 GHz to 1.7 GHz|
|L1 cache||32 KB per core|
|L2 cache||512 KB per core|
|Transistors||22 nm transistors (Tri-Gate)|
14 nm transistors (Tri-Gate)
Xeon Phi is a series of x86 manycore processors designed and made entirely by Intel. They are intended for use in supercomputers, servers, and high-end workstations. Its architecture allows use of standard programming languages and APIs such as OpenMP.
Since it was originally based on an earlier GPU design by Intel, it shares application areas with GPUs. The main difference between Xeon Phi and a GPGPU like Nvidia Tesla is that Xeon Phi, with an x86-compatible core, can, with less modification, run software that was originally targeted at a standard x86 CPU.
Initially in the form of PCIe-based add-on cards, a second generation product, codenamed Knights Landing was announced in June 2013. These second generation chips could be used as a standalone CPU, rather than just as an add-in card.
In June 2013, the Tianhe-2 supercomputer at the National Supercomputer Center in Guangzhou (NSCC-GZ) was announced as the world's fastest supercomputer (as of June 2018[update], it is No. 4). It uses Intel Xeon Phi coprocessors and Ivy Bridge-EP Xeon processors to achieve 33.86 petaFLOPS.
|Knights Ferry||45 nm||offered as PCIe card; derived from Larrabee project|
|Knights Corner||22 nm||derived from P54C; vector processing unit; first device to be announced as Xeon Phi|
|Knights Landing||14 nm||Abbr.: KNL; derived from Silvermont/Airmont (Intel Atom); AVX-512|
|Knights Hill||10 nm||canceled|
|Knights Mill||14 nm||nearly identical to Knights Landing but optimized for deep learning|
The Larrabee microarchitecture (in development since 2006) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing, the Larrabee chips also included specialised hardware for texture sampling. The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010.
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single-chip Cloud Computer' (prototype introduced 2009), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for inter-chip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.
The Teraflops Research Chip (prototype unveiled 2007) is an experimental 80-core chip with two floating point units per core, implementing a 96-bit VLIW architecture instead of the x86 architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.
Intel's Many Integrated Core (MIC) prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced May 31, 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.
The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 KB per core with 32 KB L1 cache), and a power requirement of ~300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory. Single board performance has exceeded 750 GFLOPS. The prototype boards only support single precision floating point instructions.
Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.
In June 2011, SGI announced a partnership with Intel to use the MIC architecture in its high performance computing products. In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10 petaFLOPS "Stampede" supercomputer, providing 8 petaFLOPS of compute power. According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."
On June 5, 2012, Intel released open source software and documentation regarding Knights Corner.
On June 18, 2012, Intel announced at the 2012 Hamburg International Supercomputing Conference that Xeon Phi will be the brand name used for all products based on their Many Integrated Core architecture. In June 2012, Cray announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems.
In June 2012, ScaleMP announced a virtualization update allowing Xeon Phi as a transparent processor extension, allowing legacy MMX/SSE code to run without code changes. An important component of the Intel Xeon Phi coprocessor’s core is its vector processing unit (VPU). The VPU features a novel 512-bit SIMD instruction set, officially known as Intel Initial Many Core Instructions (Intel IMCI). Thus, the VPU can execute 16 single-precision (SP) or 8 double-precision (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers. The VPU also features an Extended Math Unit (EMU) that can execute operations such as reciprocal, square root, and logarithm, thereby allowing these operations to be executed in a vector fashion with high bandwidth. The EMU operates by calculating polynomial approximations of these functions.
On November 12, 2012, Intel announced two Xeon Phi coprocessor families using the 22 nm process size: the Xeon Phi 3100 and the Xeon Phi 5110P. The Xeon Phi 3100 will be capable of more than 1 teraFLOPS of double precision floating point instructions with 240 GB/sec memory bandwidth at 300 W. The Xeon Phi 5110P will be capable of 1.01 teraFLOPS of double precision floating point instructions with 320 GB/sec memory bandwidth at 225 W. The Xeon Phi 7120P will be capable of 1.2 teraFLOPS of double precision floating point instructions with 352 GB/sec memory bandwidth at 300 W.
On June 17, 2013, the Tianhe-2 supercomputer was announced by TOP500 as the world's fastest. Tianhe-2 used Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 petaFLOPS. It was the fastest on the list for two and a half years, lastly in November 2015.
Design and programming
The cores of Knights Corner are based on a modified version of P54C design, used in the original Pentium. The basis of the Intel MIC architecture is to leverage x86 legacy by creating an x86-compatible multiprocessor architecture that can use existing parallelization software tools. Programming tools include OpenMP, OpenCL, Cilk/Cilk Plus and specialised versions of Intel's Fortran, C++ and math libraries.
Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core), and ultra-wide ring bus connecting processors and memory.
|Xeon Phi 3110X||SE3110X||61 (244)||1053||-||30.5 MB||6 GB||
|240||1028||300||Bare board||PCIe 2.0 x16 card||???|
|Xeon Phi 3120A||SC3120A||57 (228)||1100||-||28.5 MB||6 GB||6x||240||1003||300||Fan/heatsink||June 17, 2013|
|Xeon Phi 3120P ||SC3120P||57 (228)||1100||-||28.5 MB||6 GB||6x||240||1003||300||Passive heatsink||June 17, 2013|
|Xeon Phi 31S1P||BC31S1P||57 (228)||1100||-||28.5 MB||8 GB||8x||320||1003||270||Passive heatsink||June 17, 2013|
|Xeon Phi 5110P||SC5110P||60 (240)||1053||-||30.0 MB||8 GB||8x||320||1011||225||Passive heatsink||Nov 12, 2012|
|Xeon Phi 5120D||SC5120D||60 (240)||1053||-||30.0 MB||8 GB||8x||352||1011||245||Bare board||SFF 230-pin card||June 17, 2013|
|Xeon Phi SE10P||SE10P||61 (244)||1100||-||30.5 MB||8 GB||8x||352||1074||300||Passive heatsink||PCIe 2.0 x16 card||Nov. 12, 2012|
|Xeon Phi SE10X||SE10X||61 (244)||1100||-||30.5 MB||8 GB||8x||352||1074||300||Bare board||Nov. 12, 2012|
|Xeon Phi 7110P||SC7110P||61 (244)||1250||???||30.5 MB||16 GB||8x||352||1220||300||Passive heatsink||???|
|Xeon Phi 7110X||SC7110X||61 (244)||1250||???||30.5 MB||16 GB||8x||352||1220||300||Bare board||???|
|Xeon Phi 7120A||SC7120A||61 (244)||1238||1333||30.5 MB||16 GB||8x||352||1208||300||Fan/heatsink||April 6, 2014|
|Xeon Phi 7120D||SC7120D||61 (244)||1238||1333||30.5 MB||16 GB||8x||352||1208||270||Bare board||SFF 230-pin card||March ??, 2014|
|Xeon Phi 7120P||SC7120P||61 (244)||1238||1333||30.5 MB||16 GB||8x||352||1208||300||Passive heatsink||PCIe 2.0 x16 card||June 17, 2013|
|Xeon Phi 7120X||SC7120X||61 (244)||1238||1333||30.5 MB||16 GB||8x||352||1208||300||Bare board||June 17, 2013|
Code name for the second generation MIC architecture product from Intel. Intel officially first revealed details of its second generation Intel Xeon Phi products on June 17, 2013. Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's 14 nm process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth.
Knights Landing contains up to 72 Airmont (Atom) cores with four threads per core, using LGA 3647 socket supporting up to 384 GB of "far" DDR4 2133 RAM and 8–16 GB of stacked "near" 3D MCDRAM, a version of the Hybrid Memory Cube. Each core has two 512-bit vector units and supports AVX-512 SIMD instructions, specifically the Intel AVX-512 Foundational Instructions (AVX-512F) with Intel AVX-512 Conflict Detection Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF).
The National Energy Research Scientific Computing Center announced that Phase 2 of its newest supercomputing system "Cori" would use Knights Landing Xeon Phi coprocessors.
On June 20, 2016, Intel launched the Intel Xeon Phi product family x200 based on the Knights Landing architecture, stressing its applicability to not just traditional simulation workloads, but also to machine learning. The model lineup announced at launch included only Xeon Phi of bootable form-factor, but two versions of it: standard processors and processors with integrated Intel Omni-Path architecture fabric. The latter is denoted by the suffix F in the model number. Integrated fabric is expected to provide better latency at a lower cost than discrete high-performance network cards.
Intel announced the product discontinuance during Summer 2018
All models can boost to their peak speeds, adding 200 MHz to their base frequency when running just one or two cores. When running from three to the maximum number of cores, the chips can only boost 100 MHz above the base frequency. All chips run high-AVX code at a frequency reduced by 200 MHz.
|MCDRAM Memory||DDR4 Memory||Peak DP
|Xeon Phi 7210||SR2ME (B0)||64 (256)||1300||1500||32 MB||16 GB||400+ GB/s||384 GB||102.4 GB/s||2662
|Xeon Phi 7210F||SR2X5 (B0)||230||HJ8066702975000|
|Xeon Phi 7230||SR2MF (B0)||215||HJ8066702859400|
|Xeon Phi 7230F||SR2X2 (B0)||230||HJ8066702269002|
|Xeon Phi 7250||SR2MD (B0)||68 (272)||1400||1600||34 MB||3046
|Xeon Phi 7250F||SR2X0 (B0)||230||HJ8066702268900|
|Xeon Phi 7290||SR2WY (B0)||72 (288)||1500||1700||36 MB||3456
|Xeon Phi 7290F||SR2WZ (B0)||260||HJ8066702975200|
Knights Hill was expected to be used in the United States Department of Energy Aurora supercomputer, to be deployed at Argonne National Laboratory. However, Aurora was delayed in favor of using an "advanced architecture" with a focus on machine learning.
In 2017, Intel announced that Knights Hill had been canceled in favor of another architecture built from the ground up to enable Exascale computing in the future. This new architecture in now expected for 2020–2021. The terms Exascale computing and high performance computing (HPC) got meanwhile linked by intel towards their own term Omni-Path Architecture (OPA) in publications.
Knights Mill is Intel's codename for a Xeon Phi product specialized in deep learning, initially released in December 2017. Nearly identical in specifications to Knights Landing, Knights Mill includes optimizations for better utilization of AVX-512 instructions and enables 4-way hyperthreading. Single-precision and variable-precision floating-point performance increased, at the expense of double-precision floating-point performance.
|MCDRAM Memory||DDR4 Memory||Peak DP
|Xeon Phi 7235||TBA||64 (256)||1300||1400||32 MB||16 GB||400+ GB/s||384 GB||102.4 GB/s||TBA||250||
|Xeon Phi 7285||TBA||68 (272)||1300||1400||34 MB||115.2 GB/s||TBA||250||TBA|
|Xeon Phi 7295||TBA||72 (288)||1500||1600||36 MB||115.2 GB/s||TBA||320||TBA|
An empirical performance and programmability study has been performed by researchers, in which the authors claim that achieving high performance with Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is still far from reality. However, research in various domains, such as life sciences, deep learning and computer-aided engineering demonstrated that exploiting both the thread- and SIMD-parallelism of Xeon Phi achieves significant speed-ups.
- Nvidia Tesla, a direct competitor in the HPC market
- AMD Radeon Pro and AMD Radeon Instinct direct competitors in the HPC market
- Texas Advanced Computing Center – "Stampede" supercomputer incorporates Xeon Phi chips. Stampede is capable of 10 petaFLOPS.
- Radek (June 18, 2012). "Chip Shot: Intel Names the Technology to Revolutionize the Future of HPC - Intel Xeon Phi Product Family". Intel. Retrieved December 12, 2012.
- "TOP500 - June 2013". TOP500 - June 2013. TOP500. Retrieved June 18, 2013.
- "June 2018 | TOP500 Supercomputer Sites". www.top500.org. Retrieved 2018-07-22.
- "Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies". Retrieved June 21, 2013.
- Charlie Demerjian (July 3, 2006), "New from Intel: It's Mini-Cores!", www.theinquirer.net, The Inquirer
- Seiler, L.; Cavin, D.; Espasa, E.; Grochowski, T.; Juan, M.; Hanrahan, P.; Carmean, S.; Sprangle, A.; Forsyth, J.; Abrash, R.; Dubey, R.; Junkins, E.; Lake, T.; Sugerman, P. (August 2008). "Larrabee: A Many-Core x86 Architecture for Visual Computing" (PDF). ACM Transactions on Graphics. Proceedings of ACM SIGGRAPH 2008. 27 (3): 18:11–18:11. doi:10.1145/1360612.1360617. ISSN 0730-0301. Retrieved 2008-08-06.
- Tom Forsyth, "SIMD Programming with Larrabee" (PDF), www.stanford.edu, Intel
- Ryan Smith (May 25, 2010), "Intel Kills Larrabee GPU, Will Not Bring a Discrete Graphics Product to Market\", www.anandtech.com, AnandTech
- Tony Bradley (December 3, 2009), "Intel 48-Core "Single-Chip Cloud Computer" Improves Power Efficiency", www.pcworld.com, PCWorld
- "Intel Research : Single-Chip Cloud Computer", techresearch.intel.com, Intel
- Ben Ames (February 11, 2007), "Intel Tests Chip Design With 80-Core Processor", www.pcworld.com, IDG News
- "Intel Details 80-Core Teraflops Research Chip - X-bit labs". xbitlabs.com. Archived from the original on 5 February 2015. Retrieved 27 August 2015.
- "Intel's Teraflops Research Chip" (PDF), download.intel.com, Intel
- Anton Shilov (12 February 2007), "Intel Details 80-Core Teraflops Research Chip", www.xbitlabs.com, Xbit laboratories, archived from the original on 5 February 2015
- Rupert Goodwins (June 1, 2010), "Intel unveils many-core Knights platform for HPC", www.zdnet.co.uk, ZDNet
- "Intel News Release : Intel Unveils New Product Plans dor High-Performance Computing", www.intel.com, Intel, May 31, 2010
- Mike Giles (June 24, 2010), "Runners and riders in GPU steeplechase" (PDF), people.maths.ox.ac.uk, pp. 8–10
- Gareth Halfacree (June 20, 2011), "Intel pushes for HPC space with Knights Corner", www.thinq.co.uk, Net Communities Limited, UK
- "Intel Many Integrated Core Architecture" (PDF), www.many-core.group.cam.ac.uk, Intel, December 2010, archived from the original (PDF) on 2 April 2012
- Rick Merritt (June 20, 2011), "OEMs show systems with Intel MIC chips", www.eetimes.com, EE Times
- Tom R. Halfhill (July 18, 2011), "Intel Shows MIC Progress", www.linleygroup.com, The Linley Group
- Andrea Petrou (20 June 2011), "SGI wants Intel for super supercomputer", news.techeye.net, archived from the original on 16 September 2011
- ""Stampede's" Comprehensive Capabilities to Bolster U.S. Open Science Computational Resources", www.tacc.utexas.edu, Texas Advanced Computing Center, September 22, 2011
- "Stampede: A Comprehensive Petascale Computing Environment" (PDF). IEEE Cluster 2011 Special Topic. Archived from the original (PDF) on 26 September 2012. Retrieved 16 November 2011.
- Yam, Marcus (November 16, 2011), "Intel's Knights Corner: 50+ Core 22nm Co-processor", www.tomshardware.com, Tom's Hardware, retrieved November 16, 2011
- Sylvie Barak (November 16, 2011), "Intel unveils 1 TFLOP/s Knights Corner", www.eetimes.com, EE Times, retrieved November 16, 2011
- James Reinders (June 5, 2012), Knights Corner: Open source software stack, Intel
- Prickett Morgan, Timothy (June 18, 2012), "Intel slaps Xeon Phi brand on MIC coprocessors", 222.theregister.co.uk
- Intel Corporation (June 18, 2012), "Latest Intel Xeon Processors E5 Product Family Achieves Fastest Adoption of New Technology on Top500 List", www.marketwatch.com,
Intel Xeon Phi is the new brand name for all future Intel Many Integrated Core Architecture based products targeted at HPC, enterprise, datacenters and workstations. The first Intel Xeon Phi product family member is scheduled for volume production by the end of 2012
- Raj Hazra (June 18, 2012). "Intel Xeon Phi coprocessors accelerate the pace of discovery and innovation". Intel. Retrieved December 12, 2012.
- Rick Merritt (June 18, 2012). "Cray will use Intel MIC, branded Xeon Phi". EETimes. Retrieved December 12, 2012.
- Terrence O'Brien (June 18, 2012). "Intel christens its 'Many Integrated Core' products Xeon Phi, eyes exascale milestone". Engadget. Retrieved December 12, 2012.
- Jeffrey Burt (June 18, 2012). "Intel Wraps Xeon Phi Branding Around MIC Coprocessors". EWeek. Retrieved December 12, 2012.
- Merritt, Rick (June 8, 2012), "Cray will use Intel MIC, branded Xeon Phi", www.eetimes.com
- Latif, Lawrence (June 19, 2012), "Cray to support Intel's Xeon Phi in Cascade clusters", www.theinquirer.net
- "ScaleMP vSMP Foundation to Support Intel Xeon Phi", www.ScaleMP.com, ScaleMP, June 20, 2012
- IntelPR (November 12, 2012). "Intel Delivers New Architecture for Discovery with Intel Xeon Phi Coprocessors". Intel. Retrieved December 12, 2012.
- Agam Shah (November 12, 2012). "Intel ships 60-core Xeon Phi processor". Computerworld. Retrieved December 12, 2012.
- Johan De Gelas (November 14, 2012). "The Xeon Phi at work at TACC". AnandTech. Retrieved December 12, 2012.
- "Tianhe-2 (MilkyWay-2)". Top500.org. November 14, 2015. Retrieved May 6, 2016.
- Hruska, Joel (July 30, 2012). "Intel's 50-core champion: In-depth on Xeon Phi". ExtremeTech. Ziff Davis, Inc. Retrieved December 2, 2012.
- Barker, J; Bowden, J (2013). "Manycore Parallelism through OpenMP". OpenMP in the Era of Low Power Devices and Accelerators. IWOMP. Lecture Notes in Computer Science, vol 8122. Springer.
- Rick Merritt (June 20, 2011), "OEMs show systems with Intel MIC chips", www.eetimes.com, EE Times
- Efficient Hybrid Execution of C++ Applications using Intel Xeon Phi Coprocessor, November 23, 2012, arXiv:1211.5530, Bibcode:2012arXiv1211.5530D
- "News Fact Sheet: Intel Many Integrated Core (Intel MIC) Architecture ISC'11 Demos and Performance Description" (PDF), newsroom.intel.com, Intel, June 20, 2011, archived from the original (PDF) on March 24, 2012
- Tesla vs. Xeon Phi vs. Radeon. A Compiler Writer’s Perspective // The Portland Group (PGI), CUG 2013 Proceedings
- "Intel Many Integrated Core Architecture (Intel MIC Architecture) - RESOURCES (including downloads)". Intel. Retrieved January 6, 2014.
- "Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual" (PDF). Intel. September 7, 2012. Retrieved January 6, 2014.
- "Intel Developer Zone: Intel Xeon Phi Coprocessor". Intel. Retrieved January 6, 2014.
- "Intel SE3110X Xeon Phi 3110X Knights Corner 6GB Coprocessor-No Cooling -SabrePC.com -SabrePC.com". www.sabrepc.com. Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 3120A (6GB, 1.100 GHz, 57 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 3120P (6GB, 1.100 GHz, 57 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi 31S1P - BC31S1P". www.cpu-world.com. Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 5110P (8GB, 1.053 GHz, 60 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 5120D (8GB, 1.053 GHz, 60 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi SE10P". www.cpu-world.com. Retrieved 2017-02-22.
- "Intel Xeon Phi SE10X". www.cpu-world.com. Retrieved 2017-02-22.
- "Intel SC7110P Xeon Phi 7110P Knights Corner Coprocessor -SabrePC.com -SabrePC.com". www.sabrepc.com. Retrieved 2017-02-22.
- "Intel SC7110X Xeon Phi 7110X Knights Corner Coprocessor -SabrePC.com -SabrePC.com". www.sabrepc.com. Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 7120A (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 7120D (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 7120P (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Coprocessor 7120X (16GB, 1.238 GHz, 61 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi 'Knights Landing' Features Integrated Memory With 500 GB/s Bandwidth and DDR4 Memory Support - Architecture Detailed". WCCFtech. Retrieved August 27, 2015.
- Sebastian Anthony (November 26, 2013), Intel unveils 72-core x86 Knights Landing CPU for exascale supercomputing, ExtremeTech
- Tom's Hardware: Intel Xeon Phi Knights Landing Now Shipping; Omni Path Update, Too. June 20, 2016
- James Reinders (July 23, 2013), AVX-512 Instructions, Intel
- 2016 ISC High Performance: Intel's Rajeeb Hazra Delivers Keynote Address
- How Intel Xeon Phi Processors Benefit Machine Learning/Deep Learning Apps and Frameworks
- Introducing the Intel Xeon Phi Processor – Your Path to Deeper Insight
- Larabel, Michael (24 August 2017). "Intel Quietly Drops Xeon Phi 7200 Coprocessors". Phoronix. Retrieved 25 August 2017.
- "Product Change Notification 116378 - 00" (PDF). Intel.com. Retrieved 25 July 2018.
- "Intel Xeon Phi processor: Your Path to Deeper Insight" (PDF). Intel.com. Retrieved February 25, 2017.
- "Intel Xeon Phi Processor 7210 (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Processor 7210F (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Processor 7230 (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Processor 7230F (16GB, 1.30 GHz, 64 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Processor 7250 (16GB, 1.40 GHz, 68 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Processors". Intel. Retrieved 2017-02-25.
- "Intel Xeon Phi Processor 7250F (16GB, 1.40 GHz, 68 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Processor 7290 (16GB, 1.50 GHz, 72 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- "Intel Xeon Phi Processor 7290F (16GB, 1.50 GHz, 72 core) Product Specifications". Intel ARK (Product Specs). Retrieved 2017-02-22.
- SC14: Supercomputing '14; International Conference for High Performance Computing, Networking, Storage and Analysis in year 2014
- Eric Gardner (November 25, 2014), What public disclosures has Intel made about Knights Landing?, Intel Corporation
- ALCF staff (April 9, 2015), Introducing Aurora
- ALCF staff (April 9, 2015), Aurora
- Hemsoth, Nicole (23 May 2017). "Some Surprises in the 2018 DoE Budget for Supercomputing". Next Platform. Retrieved 13 November 2017.
- Brueckner, Rich (16 June 2017). "Is Aurora Morphing into an Exascale AI Supercomputer?". Inside HPC. Retrieved 13 November 2017.
- Damkroger, Trish (13 November 2017). "Unleashing high performance computing today and tomorrow". Intel IT Peer Network.
- Kampman, Jeff (13 November 2017). "Intel quietly kills off next-gen Knights Hill Xeon Phi chips". Tech Report. Retrieved 13 November 2017.
- Intel® Omni-Path Architecture (Intel® OPA) Driving Exascale Computing and HPC; Driving Exascale Computing and HPC with Intel, intel publication without a date
- Smith, Ryan (17 August 2016). "Intel Announces Knight's Mill: A Xeon Phi for Deep Learning". Anandtech. Retrieved 17 August 2016.
- Cutress, Ian (19 December 2017). "Intel Lists Knights Mill Xeon Phi on ARK: Up to 72 cores at 320W with QFMA and VNNI". Anandtech. Retrieved 19 December 2017.
- Fang, Jianbin; Sips, Henk; Zhang, Lilun; Xu, Chuanfu; Yonggang, Che; Varbanescu, Ana Lucia (2014). "Test-Driving Intel Xeon Phi" (PDF). Retrieved December 30, 2013.[dead link]
- Accelerating DNA Sequence Analysis using Intel Xeon Phi, June 29, 2015, arXiv:1506.08612, Bibcode:2015arXiv150608612M
- The Potential of the Intel Xeon Phi for Supervised Deep Learning, June 30, 2015, arXiv:1506.09067, Bibcode:2015arXiv150609067V
- Margetts, L.; Arregui-Mena, J.D.; Hewitt, W.T.; Mason, L. (2–3 June 2016). Parallel finite element analysis using the Intel Xeon Phi. Emerging Technology Conference EMiT2016. Barcelona, Spain.
- Jon Stokes (June 20, 2011). "Intel takes wraps off 50-core supercomputing processor plans". Ars Technica.
- Johan De Gelas (September 11, 2012). "Intel's Xeon Phi in 10 Petaflops supercomputer". AnandTech. Retrieved December 12, 2012.
|Wikimedia Commons has media related to Intel MIC.|
- Intel pages: Xeon Phi Product Family