Intel i960

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Intel i960
KL Intel i960 PGA.jpg
Intel i960HA microprocessor
General information
Common manufacturer(s)
  • Intel
Max. CPU clock rate10 MHz to 100 MHz
Physical specifications
  • 1

Intel's i960 (or 80960) was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000.[2] In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.


Intel N80960SA (PLCC Package)
Intel GC80960RD66 (BGA Package)
Intel GC80960RN, sSpec: SL3YW, BGA Package
Intel FC80960HD66 (PQFP Package)

The i960 design was begun in response to the failure of Intel's iAPX 432 design of the early 1980s. The iAPX 432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory—such as Ada and Lisp—in hardware. Because of its instruction-set complexity, its multi-chip implementation, and design flaws, the iAPX 432 was very slow in comparison to other processors of its time.

In 1984, Intel and Siemens started a joint project, ultimately called BiiN, to create a high-end, fault-tolerant, object-oriented computer system programmed entirely in Ada. Many of the original i432 team members joined this project, although a new lead architect, Glenford Myers, was brought in from IBM. The intended market for the BiiN systems was high-reliability-computer users such as banks, industrial systems, and nuclear power plants.

Intel's major contribution to the BiiN system was a new processor design, influenced by the protected-memory concepts from the i432. The new design was to include a number of features to improve performance and avoid problems that had led to the i432's downfall. The first 960 processors entered the final stages of design, known as taping-out, in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986.

The BiiN effort eventually failed, due to market forces, and the 960MX was left without a use. Myers attempted to save the design by extracting several subsets of the full capability architecture created for the BiiN system. He tried to convince Intel management to market the i960 (then still known as the "P7") as a general-purpose processor, both in place of the Intel 80286 and i386 (which taped-out the same month as the first i960), as well as the emerging RISC market for Unix systems, including a pitch to Steve Jobs for use in the NeXT system. Competition within and outside of Intel came not only from the i386 camp but also from the i860 processor, yet another RISC processor design emerging within Intel at the time[dubious ][citation needed]. Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems.

The lead architect of i960 was superscalarity specialist Fred Pollack who was also the lead engineer of the Intel iAPX 432 and the lead architect of the i686 chip, the Pentium Pro.[3]


To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design, which was only implemented in full in the i960MX. The memory subsystem was 33-bits wide—to accommodate a 32-bit word and a "tag" bit to implement memory protection in hardware. In many ways, the i960 followed the original Berkeley RISC design, notably in its use of register windows, an implementation-specific number of caches for the per-subroutine registers that allowed for fast subroutine calls. The competing Stanford University design, MIPS, did not use this system, instead relying on the compiler to generate optimal subroutine call and return code. In common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no memory segmentation, except for the i960MX, which could support up to 226 "objects", each up to 232 bytes in size.[4] The i960 architecture also anticipated a superscalar implementation, with instructions being simultaneously dispatched to more than one unit within the processor.

i960 variants[edit]

80960MX, 80960MC[edit]

The "full" i960MX was never released for the non-military market, but the otherwise identical i960MC was used in high-end embedded applications. The i960MC included all of the features of the original BiiN system; but these were simply not mentioned in the specifications, leading some[who?] to wonder why the i960MC was so large and had so many pins labeled "no connect".

80960KA, 80960KB[edit]

A version of the RISC core without memory management or an FPU became the i960KA, and the RISC core with an FPU became the i960KB. The versions were, however, identical internally—only the labeling was different. This meant the CPUs were much larger than necessary for the "actually supported" feature sets, and as a result, more expensive to manufacture than they needed to be.

The i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations, which were without the complex memory sub-system.

80960CA, 80960CF[edit]

The i960CA, first announced in July 1989, was the first pure RISC implementation of the i960 architecture. It featured a newly designed superscalar RISC core and added an unusual addressable on-chip cache, but lacked an FPU and MMU, as it was intended for high-performance embedded applications. The i960CA is widely considered[by whom?] to have been the first single-chip superscalar RISC implementation. The C-series included only one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, and a branch instruction at the same time, and sustain two instructions per cycle under certain circumstances. The first versions released ran at 33 MHz, and Intel promoted the chip as capable of 66 MIPS. The i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12, 1989.

Later, in May 1992, came the i960CF, which included a larger instruction cache (4 KB instead of 1 KB) and added 1 KB of data cache, but was still without an FPU or MMU.


The 80960Jx is a processor for embedded applications. It features a 32-bit multiplexed address/data bus, instruction and data cache, 1K on-chip RAM, interrupt controller, and two independent 32-bit timers. The 80960Jx’s testability features included ONCE (on-circuit emulation) mode and boundary scan (JTAG).

80960HA, 80960HD, 80960HT[edit]

The 80960Hx processors offered upgraded performance from the Cx variants by offering clock multiplication, larger 16K instruction cache and 4k data cache, and a GMU. (Guarded Memory Unit). The HD variant had an internal 2x clock multiplication while the HT version has a 3x clock multiplication, allowing increased performance without external bus speed changes.


Announced in October 1998, the i960VH Embedded-PCI processor featured a 32-bit 33 MHz PCI bus and 100 MHz i960JT processor core. The core also featured 16 KB of instruction cache, 4 KB of data cache, and 1 KB of built-in RAM. Other core features included two 32-bit timers, programmable interrupt controller, I²C interface, and a two-channel DMA controller.


The 80960Rx processors were labeled as I/O Processors and included an implementation of the PCI Bus (2.1 or 2.2 depending on the variant) as well as a 80960Jx core. These could be used on motherboards to implement on-board PCI device as well as on PCI expansion cards. The RM/RN/RS variants used a JT core with a 3x bus to core multiplication to achieve 100 MHz internal clock speeds, while the RD variant used a JF core with 2x multiplication to achieve 66 MHz. The RP variant had a JF core that ran at the 33 MHz bus speed.

Variant specifications[edit]

  • 5V Parts
Model Number Core Frequency Bus Frequency Multiplier iCache dCache Voltage Socket
80960MC 20,25 MHz 20,25 MHz 1.0x 512B 0 5.0 V PGA-132
80960SA 10,12,16,20 MHz 10,12,16,20 MHz 1.0x 512B 0 5.0 V 80-PQFP,84-PLCC
80960SB 10,16 MHz 10,16 MHz 1.0x 512B 0 5.0 V 80-PQFP,84-PLCC
80960KA 10,20,25 MHz 10,20,25 MHz 1.0x 512B 0 5.0 V 132-PQFP,132-PGA
80960KB 16,20,25 MHz 16,20,25 MHz 1.0x 512B 0 5.0 V 132-PQFP,132-PGA
80960CA 16,25,33 MHz 16,25,33 MHz 1.0x 1KB 0 5.0 V 168-PGA,196-PQFP
80960CF 25,33,40 MHz 25,33,40 MHz 1.0x 4KB 1KB 5.0 V 168-PGA,196-PQFP
  • 3.3V Parts
Model Number Core Frequency Bus Frequency Multiplier iCache dCache Voltage Socket
80960JA 16,25,33 MHz 16,25,33 MHz 1.0x 2KB 1KB 3.3 V 132-PQFP,132-PGA
80960JF 25,33 MHz 25,33 MHz 1.0x 4KB 2KB 3.3 V 132-PQFP,132-PGA
80960JD 66,50,40,33 MHz 16,20,25,33 MHz 2.0x 4KB 2KB 3.3 V 132-PQFP,132-PGA
80960JS 25,33 MHz 25,33 MHz 1.0x 16KB 4KB 3.3 V 132-PQFP,132-PGA,196-MPBGA
80960JC 50,66 MHz 25,33 MHz 2.0x 16KB 4KB 3.3 V 132-PQFP,132-PGA,196-MPBGA
80960JT 75,100 MHz 25,33 MHz 2.0x 16KB 4KB 3.3 V 132-PQFP,132-PGA,196-MPBGA
80960HA 25,33,40 MHz 25,33,40 MHz 1.0x 16KB 8KB 3.3 V 168-PGA,208-PQ4
80960HD 50,66,80 MHz 25,33,40 MHz 2.0x 16KB 8KB 3.3 V 168-PGA,208-PQ4
80960HT 75 MHz 25 MHz 3.0x 16KB 8KB 3.3 V 168-PGA,208-PQ4
  • PCI I/O Processor Variants
Model Number Core Frequency Bus Frequency Multiplier iCache dCache PCI Version Voltage Socket
80960RP 33 MHz 33 MHz 1.0x 4KB 2KB PCI 2.1 3.3 V 352-PBGA
80960RD 33 MHz 66 MHz 2.0x 4KB 2KB PCI 2.1 3.3 V 352-PBGA
80960VH 100 MHz 33 MHz 3.0x 16KB 4KB PCI 2.1 3.3 V 324-PBGA
80960RM/N 100 MHz 33 MHz 3.0x 16KB 4KB PCI 2.1 3.3 V 540-PBGA
80960RS 100 MHz 33 MHz 3.0x 16KB 4KB PCI 2.2 3.3 V 540-PBGA
80302/3 100 MHz 66 MHz 1.5x 16KB 4KB PCI 2.2 3.3 V 540-PBGA

End of development[edit]

Intel attempted to bolster the i960 in the I/O device controller market with the I2O standard, but this had little success and the design work was eventually ended. By the mid-1990s its price/performance ratio had fallen behind competing chips of more recent design, and Intel never produced a reduced-power-consumption version that could be used in battery-powered systems.

In 1990, the i960 team was redirected to be the "second team" working in parallel on future i386 implementations—specifically the P6 processor, which later became the Pentium Pro. The i960 project was given to another smaller development team, essentially ensuring the end of its developmental life.

Current status[edit]

Because of its high performance in calculating XOR values, i960 processors, such as the 80303, are often used in controllers for higher-end, RAID-capable, SCSI-disk-array, host-adapter cards as well as Digital Equipment/Compaq/HP's high-end SCSI and DSSI, and eventually Fibre Channel HSx-series, standalone RAID controllers.[5][6]

An i960RS chip also powers Adaptec's AAR-2400A controller, which uses four commodity parallel ATA drives to build an affordable RAID-5 protected fault-tolerant storage system for small PC servers and workstations.

The i960 was also used in some Brocade Fibre Channel switches to run Fabric OS.

The i960 architecture is also used in slot machines. Currently, they are found in IGT's Stepper S2000 family and i960 video family. It was also used as the main CPU of Sega's famous Model 2 series of arcade boards.

The Indian Air Force's HAL Tejas light combat aircraft's MMR (multi-mode radar) is said to use the i960. The HAL Tejas was introduced into service in 2015.

The Indian Space Research Organisation (ISRO) is said to use the chip in its on-board computers in its launch vehicles.

The i960 processor is also used in Automatic Radar Plotting Aid (ARPA) interfacing boards in radars from Kelvin Hughes.

The chip was used on some HP X-Terminals.

Some SATA RAID controllers use Intel's 80303 IOP (Intelligent I/O Processor), which integrates a PCI-to-PCI bridge, memory controller, and a 80960JT-100 CPU core.

The chip was used on the Alcatel-Lucent 1000 ADSL broadband modem [7]


  1. ^ Smith, Tony (May 18, 2006). "Intel cashes in ancient chips". The Register. Retrieved January 24, 2020.
  2. ^ Turley, Jim (January 11, 2002). "Embedded Processors, Part One". Retrieved September 8, 2018.
  3. ^ Dvorak, John C. (2008). "Whatever Happened to The iAPX432 — Intel's Dream Chip". Retrieved September 8, 2018.
  4. ^ BiiN CPU Architecture Reference Manual (PDF). BiiN. July 1998.
  5. ^ "On Platform Storageworks Seminar notes". Archived from the original on April 25, 2012.
  6. ^ "Intel Expands I/O Building Block Family To Include Intel Integrated RAID Design Kit, Software And Controller" (Press release). SANTA CLARA, Calif.: Intel. January 19, 2000. Archived from the original on August 29, 2020. Retrieved August 29, 2020.
  7. ^ "Image of the circuit board of an Alcatel 1000 ADSL modem". Retrieved September 24, 2018.

External links[edit]