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LOCOS, short for LOCal Oxidation of Silicon, is a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si-SiO2 interface at a lower point than the rest of the silicon surface.
This technology was developed to insulate MOS transistors from each other and limit transistor cross-talk. The main goal is to create a silicon oxide insulating structure that penetrates under the surface of the wafer, so that the Si-SiO2 interface occurs at a lower point than the rest of the silicon surface. This cannot be easily achieved by etching field oxide. Thermal oxidation of selected regions surrounding transistors is used instead. The oxygen penetrates in depth of the wafer, reacts with silicon and transforms it into silicon oxide. In this way, an immersed structure is formed. For process design and analysis purposes, the oxidation of silicon surfaces can be modeled effectively using the Deal–Grove model.
Typical process steps are the following:
I. Preparation of silicon substrate (layer 1)
II. CVD of SiO2, pad/buffer oxide (layer 2)
III. CVD of Si3N4, nitride mask (layer 3)
IV. Etching of nitride layer (layer 3) and silicon oxide layer (layer 2)
V. Thermal growth of silicon oxide (structure 4)
VI. Further growth of thermal silicon oxide (structure 4)
VII. Removal of nitride mask (layer 3)
There are 4 basic layers/structures:
- Si, silicon substrate, wafer
- SiO2, buffer oxide (pad oxide), chemical vapor deposition silicon oxide
- Si3N4, nitride mask
- SiO2, insulation oxide, thermal oxidation
Function of layers and structures
The silicon wafer (layer 1) is used as a basis for building electronic structures (such as MOS transistors).
To perform local oxidation, the areas not meant to be oxidized will be coated in a material that does not permit the diffusion of oxygen at high temperatures (thermal oxidation is performed in temperatures between 800 and 1200 °C), such as silicon nitride (layer 3, step III).
During the growth of the immersed insulating thermal oxide structures (steps V and VI), the silicon nitride layer (layer 3) is pushed upwards. Without the buffer oxide (layer 2, also known as pad oxide), this would create too much tension in the Si substrate (layer 1), the plastic deformation would occur and the electronic devices would be damaged.
Therefore, a buffer oxide (layer 2) is deposed by the CVD (step II) between the Si substrate (layer 1) and the silicon nitride (layer 3). At high temperatures, the viscosity of silicon oxide decreases and the stress created between the silicon substrate (layer 1) and nitride layer (layer 3), by the growth of the thermal oxide (steps V and VI), is relieved.
The insulating structures (structure 4) are formed by thermal oxidation of silicon. During this process, the silicon wafer is "consumed" and "replaced" by silicon oxide. The volume of silicon oxide to silicon is about 2.4:1, which explains the growth of the insulation structures and the created tension.
The disadvantage of this technology is that the insulating structures are rather large, and therefore, fewer MOS transistors can be formed on one wafer.
Reduction of dimensions of insulating structures is solved by the STI (Shallow Trench Isolation, also known as Box Isolation Technique). In this process, trenches are formed and silicon dioxide is deposed inside. The LOCOS technology can't be used in this way, because of the change of the volume during the thermal oxidation, which would induce too much stress in the trenches.
- Liu, M.; Peng, J.; et al. (2016). "Two-dimensional modeling of the self-limiting oxidation in silicon and tungsten nanowires". Theoretical and Applied Mechanics Letters. 6 (5): 195–199. doi:10.1016/j.taml.2016.08.002.