A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.
The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latch-up when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.
The latch-up does not have to happen between the power rails - it can happen at any place where the required parasitic structure exists. A common cause of latch-up is a positive or negative voltage spike on an input or output pin of a digital chip that exceeds the rail voltage by more than a diode drop. Another cause is the supply voltage exceeding the absolute maximum rating, often from a transient spike in the power supply. It leads to a breakdown of an internal junction. This frequently happens in circuits which use multiple supply voltages that do not come up in the required sequence on power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage. Latch-ups can also be caused by an electrostatic discharge event.
Another common cause of latch-ups is ionizing radiation which makes this a significant issue in electronic products designed for space (or very high-altitude) applications.
High-power microwave interference can also trigger latch-ups.
Both CMOS integrated circuits and TTL integrated circuits are more susceptible to latch-up at higher temperatures.
In CMOS technology, there are a number of intrinsic bipolar junction transistors. In CMOS processes, these transistors can create problems when the combination of n-well/p-well and substrate results in the formation of parasitic n-p-n-p structures. Triggering these thyristor-like devices leads to a shorting of the Vdd and GND lines, usually resulting in destruction of the chip, or a system failure that can only be resolved by power-down. 
Consider the n-well structure in the first figure. The n-p-n-p structure is formed by the source of the NMOS, the p-substrate, the n-well and the source of the PMOS. A circuit equivalent is also shown. When one of the two bipolar transistors gets forward biased (due to current flowing through the well, or substrate), it feeds the base of the other transistor. This positive feedback increases the current until the circuit fails or burns out.
The invention of the now industry-standard technique to prevent CMOS latch-up was made by Hughes Aircraft company in 1977.
It is possible to design chips to be resistant to latch-up by adding a layer of insulating oxide (called a trench) that surrounds both the NMOS and the PMOS transistors. This breaks the parasitic SCR structure between these transistors. Such parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed, such as hot swap devices.
Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are also less susceptible to latch-up. The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine.
Another possibility for a latch-up prevention is the Latch-up Protection Technology circuit. When a latch-up is detected, the LPT circuit shuts down the chip and holds it powered-down for a preset time.
Also to avoid the latch, a separate tap connection is put for each transistor. But this will increase the size of the device so fabs give a minimum space to put a tap, for example, 10 µm in 130 nm technology.[clarification needed]
Testing for latch-up
- See EIA/JEDEC STANDARD IC Latch-Up Test EIA/JESD78.
This standard is commonly referenced in IC qualification specifications.
- R. Koga, K.B. Crawford, S.J. Hansel, B.M. Johnson, D.D. Lau, S.H. Penzin, S.D. Pinkerton, M.C. Maher. "AN-932 SEU and Latch Up Tolerant Advanced CMOS Technology". 1994.
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- Cooper, M.S.; Retzler, J.P. "High Temperature Schottky TTL latch-up". doi: 10.1109/TNS.1978.4329568 1978.
- "Understanding Latch-Up in Advanced CMOS Logic". quote: "structures used in all CMOS ICs ... have latch-up paths associated with them"
- Jerry C. Whitaker. "Microelectronics 2nd Edition". 2005. p. 7-7 to 7-8. quote: "CMOS inverters and gates inherently have ... parasitic bipolar transistors that form a silicon controlled rectifier (SCR). Although ... latch-up cannot be avoided, CMOS manufacturers design input and output circuits that are latch-up resistant"
- Fairchild. "Fairchild's Process Enhancements Eliminate the CMOS SCR Latch-Up Problem In 74HC Logic". 1998.
- Jan M. Rabaey, University of California,Berkeley;Anantha Chandrakasan, Massachusetts Institute of Technology,Cambridge;Borivoje Nikolic, University of California, Berkeley; Digital Integrated Circuits (2nd Edition) ISBN 978-0-13-090996-1
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- Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford University Press (Indian Edition 2007) p.461 ISBN 978-0-19-568144-4