List of Intel CPU microarchitectures

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The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick-Tock model.

x86 microarchitectures[edit]

Year Micro-architecture Pipeline stages max. Clock Tech process
1989 486 (80486) 03 0100 MHz 1 µm
1993 P5 (Pentium) 05 0300 MHz 0.6 µm
1995 P6 (Pentium Pro;
later Pentium II)
14 (17 with load & store/retire)[further explanation needed] 0450 MHz 350 nm
1999 P6 (Pentium III)

(Copper Mine)

12 (15 with load & store/retire) 0450–
1400 MHz
250 nm
2000 NetBurst
(Pentium 4)(Willamette) and (Northwood)
20 unified with branch prediction 0800–
3466 MHz
180 nm
2003 Pentium M 10 (12 with fetch/retire)[further explanation needed] 0400–
2133 MHz
130 nm
2004 Prescott
(NetBurst)
31 unified with branch prediction 3800 MHz 90 nm
2006 Intel Core 12 (14 with fetch/retire) 3000 MHz 65 nm
2007 Penryn 3333 MHz 45 nm
2008 Nehalem 20 unified (14 without miss prediction) 3600 MHz
Bonnell 16 (20 with prediction miss) 2100 MHz
2010 Westmere 20 unified (14 without miss prediction) 3730 MHz 32 nm
2011 Saltwell 2130 MHz
Sandy Bridge 14 (16 with fetch/retire) 4000 MHz
2012 Ivy Bridge 14 (16 with fetch/retire) 4100 MHz 22 nm
2013 Silvermont 14-17 (16-19 with fetch/retire) 2670 MHz
Haswell 14 (16 with fetch/retire) 4400 MHz
2014 Broadwell 14 (16 with fetch/retire) 3700 MHz 14 nm
2015 Skylake 14 (16 with fetch/retire) 4200 MHz
2016 Goldmont 20 unified with branch prediction 2600 MHz
Kaby Lake 14 (16 with fetch/retire) 4500 MHz
2017 Coffee Lake 14 (16 with fetch/retire) 4800 MHz
Goldmont Plus ? 20 unified with branch prediction ? 2800 MHz
2018 Cannon Lake 14 (16 with fetch/retire) 10 nm
Cascade Lake 14 ? MHz 14 nm
Whiskey Lake
2019 Ice Lake 10 nm
Before P5
  • 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.
  • 186: included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions.
  • 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.
  • i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
  • i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
P5
original Pentium microprocessors, first x86 processor with super-scalar architecture, branch prediction and RISC µop decode scheme.
P6
used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
NetBurst
Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.
Pentium M
updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
Intel Core
reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
Nehalem
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Bonnell
45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
Sandy Bridge
released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
  • Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.
Silvermont
22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
Haswell
22 nm microarchitecture, released June 3, 2013. Added a number of important powerful new instructions, including FMA.
  • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
Skylake
new 14 nm microarchitecture, released August 5, 2015.
Goldmont
14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released April 2016.[2][3]
  • Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released December 11, 2017.
Ice Lake
new 10 nm microarchitecture, expected in 2019.
  • Tiger Lake: an update of Ice Lake, expected in 2020?

Itanium microarchitectures[edit]

Merced
original Itanium microarchitecture. Used only in the first Itanium microprocessors.
McKinley
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
Montecito
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
Tukwila
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
Poulson
Itanium processor featuring a new microarchitecture.[4]
Kittson
the last Itanium microarchitecture. It has slightly higher clock speed than Poulson.

Roadmap[edit]

Pentium 4 / Core Lines[edit]

Pentium 4 / Core Roadmap
Fabri-
cation
process
Micro-
archi-
tecture
Code
names
Core i

Generation

Release
date
Processors
8P/4P
Server
4P/2P
Server/WS
Enthusiast/
WS
Desktop Mobile
180 nm P6,
NetBurst
Willamette N/A 2000-11-20 Foster Willamette
130 nm Northwood/
Mobile Pentium 4
2002-01-07 Prestonia
Gallatin
Northwood
090 nm Prescott 2004-02-01 Nocona
Irwindale
Paxville
Prescott
065 nm Presler,
Cedar Mill,
Yonah
2006-01-05 Smithfield,

Dempsey,

Sossaman

Presler Cedar Mill Yonah
Core Merom[5] 2006-07-27[6][7] Tigerton Woodcrest
Clovertown
Kentsfield Conroe Merom
045 nm Penryn 2007-11-11
[8]
Dunnington Harpertown Yorkfield Wolfdale Penryn
Nehalem Nehalem Previous[9] 2008-11-17
[10]
Beckton Gainestown Bloomfield Lynnfield Clarksfield
032 nm Westmere 2010-01-04
[11][12]
Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Sandy
Bridge
Sandy Bridge 2 2011-01-09
[13]
[14] Sandy Bridge-EP Sandy Bridge-E Sandy Bridge Sandy Bridge-M
022 nm[15] Ivy Bridge 3 2012-04-29 Ivy Bridge-EX
[16]
Ivy Bridge-EP
[16]
Ivy Bridge-E
[17]
Ivy Bridge Ivy Bridge-M
Haswell Haswell 4 2013-06-02 Haswell-EX Haswell-EP Haswell-E Haswell-DT
[18]
Haswell-MB (37–57W TDP, PGA package)
Haswell-H (47W TDP, BGA package)
Haswell-ULP/ULX (11.5–15W TDP)[18]
Devil's
Canyon
[19]
2014-06 Haswell-DT
014 nm[15] Broadwell[20] 5 2014-09-05 Broadwell-EX
[21]
Broadwell-EP
[21]
Broadwell-E Broadwell-DT Broadwell-H (37–47W TDP)
Broadwell-U (15–28W TDP)
Broadwell-Y (4.5W TDP)
Skylake
[20]
Skylake[20] 6 2015-08-05
[22]
Skylake-SP
(formerly
Skylake-EX)
Skylake-SP
(formerly
Skylake-EP) [23]
Skylake-X [24]
Skylake-W
Skylake-S Skylake-H (35–45W TDP)
Skylake-U (15–28W TDP)
Skylake-Y (4.5W TDP)
Kaby Lake[25] 7 2016-10 Kaby Lake-X
[24]
Kaby Lake-S Kaby Lake-H (35–45W TDP)
Kaby Lake-U (15–28W TDP)
Kaby Lake-Y (4.5W TDP)
Kaby Lake
Refresh
8 2017-09
Coffee Lake 2017-10
[26]
Coffee Lake-S Coffee Lake-H
Coffee Lake-U
Kaby Lake G 2018-01-07[27]
Cascade Lake 2018 Cascade Lake-SP Cascade Lake-X
Whiskey Lake 2018 Whiskey Lake-U
? Amber Lake[28][29][30] 2018 ? Amber Lake-Y
010 nm[31] Cannon Lake 8 2018-05
Ice
Lake
[32]
Ice Lake[33] 2019
Tiger Lake[32] 2020 ?
007 nm[31]
005 nm[31]

Atom Lines[edit]

Atom Roadmap[34]
Fabri-
cation
process
Micro-
archi-
tecture
Release
date
Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server Communication CE
45 nm Bonnell 2008 Silverthorne N/A Diamondville Tunnel Creek,
Stellarton
N/A Sodaville
2010 Lincroft Pineview Groveland
32 nm Saltwell 2011 Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview)
Clover Trail (Cloverview) Cedar Trail (Cedarview) Unknown Centerton & Briarwood Unknown Berryville
22 nm Silvermont 2013 Merrifield (Tangier) [35], Slayton,
Moorefield (Anniedale)[36]
Bay Trail-T
(Valleyview)
Bay Trail-M
(Valleyview)
Bay Trail-D
(Valleyview)
Bay Trail-I
(Valleyview)
Avoton Rangeley Unknown
014 nm[34] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview) [37] Braswell [38] Denverton Cancelled Unknown Unknown
Goldmont
[39]
2016 Broxton Cancelled Willow Trail Cancelled
Apollo Lake
Apollo Lake [40] Denverton [41] Unknown Unknown
Goldmont
Plus
[42]
2017 Unknown Unknown Gemini Lake[43] Unknown Unknown Unknown
10 nm Tremont Unknown Unknown Unknown Mercury Lake Unknown Unknown Unknown

See also[edit]

References[edit]

  1. ^ "An Update On Our Graphics-related Programs". May 25, 2010. 
  2. ^ "Intel Software Development Emulator". 
  3. ^ ""Goldmont"- the sequel to Silvermont Atom?". 
  4. ^ Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. Archived from the original on October 5, 2007. Retrieved 2007-10-05. 
  5. ^ Crothers, Brooke (2009-02-10). "Intel moves up rollout of new chips | Nanotech - The Circuits Blog - CNET News". News.cnet.com. Retrieved 2014-02-25. 
  6. ^ "Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing". 
  7. ^ "Intel Unveils World's Best Processor". 
  8. ^ "Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology". 
  9. ^ "ARK | Your source for information on Intel® products". Intel. 2013-05-30. Archived from the original on 2013-05-30. Retrieved 2013-05-30. 
  10. ^ "Intel Launches Fastest Processor on the Planet". www.intel.com. 
  11. ^ Mark Bohr (Intel Senior Fellow, Logic Technology Development) (2009-02-10). "Intel 32nm Technology" (PDF). 
  12. ^ "Intel - Data Center Solutions, IoT, and PC Innovation". Intel. 
  13. ^ "Intel Sandy Bridge chip coming January 5". 
  14. ^ Pop, Sebastian. "Intel Ivy Bridge CPU Range Complete by Next Year". 
  15. ^ a b "22nm technology. May 2011" (PDF). 
  16. ^ a b "Ivy Bridge EP and EX coming up in a year's time - the multi-socket platform heaven". 9 April 2012. 
  17. ^ "Ivy Bridge-E delayed until second half of 2013". 
  18. ^ a b "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. Retrieved 2014-02-25. 
  19. ^ "Devils Canyon mit bis zu 4,4 GHz, ohne verlöteten Deckel". golem.de. Jun 3, 2014. 
  20. ^ a b c "After Intel's Haswell comes Broadwell, Sk……". 31 March 2011. 
  21. ^ a b "Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015 - KitGuru". www.kitguru.net. 
  22. ^ "The wait for Skylake is almost over, first desktop chips likely to hit August 5". 6 July 2015. 
  23. ^ Windeck, Christof. "Intel Xeon Gold, Platinum: Skylake-SP für Server "Mitte Sommer"". heise.de. Retrieved 2 May 2017. 
  24. ^ a b Mujtaba, Hassan. "Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June". wccftech.com. Retrieved 2 May 2017. 
  25. ^ "Intel confirms tick-tock shattering Kaby Lake processor as Moore's Law falters". ArsTechnica.com. Jul 15, 2015. the switch to 10nm manufacturing has been delayed until the second half of 2017. 
  26. ^ "Coffee Lake: Intels 6C-Prozessoren erfordern neue Boards - Golem.de". 
  27. ^ "New 8th Gen Intel Core Processors with Radeon RX Vega M Graphics Offer 3x Boost in Frames per Second in Devices as Thin as 17 mm". Intel Newsroom. 2018-01-07. Retrieved 2018-05-12. 
  28. ^ https://www.computerbase.de/2018-06/intel-cascade-lake-x-coffee-lake-s/
  29. ^ https://www.computerbase.de/2018-07/intel-core-i7-8565-i5-8265/
  30. ^ https://patchwork.kernel.org/patch/10475645/
  31. ^ a b c "Intel currently developing 14nm, aiming towards 5nm chips - CPU - News". HEXUS.net. 2012-05-15. Retrieved 2014-02-25. 
  32. ^ a b "Intel's Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2018 and 10nm Tiger Lake Family in 2019". WCCFTech. 2016-01-20. 
  33. ^ Eassa, Ashraf. "What's the Name of Intel's Third 10-Nanometer Chip?". 
  34. ^ a b "Intel's Silvermont Architecture Revealed: Getting Serious About Mobile". AnandTech. 
  35. ^ Hiroshige, Goto. "Intel Products for Tablets & SmartPhones" (PDF). 標準. Impress. Archived from the original (PDF) on 2013-11-14. 
  36. ^ "Import Data and Price of anniedale". 
  37. ^ "アウトオブオーダーと最新プロセスを採用する今後のAtom". 
  38. ^ "Products (Formerly Braswell)". Intel® ARK (Product Specs). Retrieved 5 April 2016. 
  39. ^ Smith, Ryan; Cutress, Ian (29 April 2016). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled". Anandtech.com. Retrieved 29 June 2016. 
  40. ^ "Products (Formerly Apollo Lake)". Intel® ARK (Product Specs). Retrieved 6 January 2016. 
  41. ^ "Products (Formerly Denverton)". Intel® ARK (Product Specs). Retrieved 6 January 2016. 
  42. ^ https://www.anandtech.com/show/12146/intel-launches-gemini-lake-pentium-silver-and-celeron-socs-new-cpu-media-features
  43. ^ "Products (Formerly Gemini Lake)". Intel® ARK (Product Specs). Retrieved 11 December 2017. 

External links[edit]