List of VIA microprocessor cores

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This page lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common.

Cyrix design (Cyrix III)[edit]

Marketing
name
Core Frequency Front-side bus L1-cache L2-cache FPU
speed
Pipeline
stages
Typical power Voltage Process
Cyrix III Joshua 350-450 MHz 100-133 MHz 64 KB 256 KB 100% ? 13-16 W 2.2 V 180 nm Al

Centaur Technology design[edit]

Cyrix III, C3[edit]

Marketing
name
Core Frequency Front-side bus L1 cache L2 cache FPU
speed
Pipeline
stages
Typical power Voltage Process
Cyrix III, C3, 1GigaPro Samuel (C5A) 466-733 MHz 100-133 MHz 128 KB 0 KB 50% 12 6.8-10.6 W 1.8-2.0 V 180 nm Al
Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+ Samuel 2 (C5B) 600-800 MHz 100-133 MHz 128 KB 64 KB 50% 12 5.8-6.6 W 1.5-1.65 V 150 nm Al
C3, Eden ESP Ezra (C5C) 733-933 MHz 100-133 MHz 128 KB 64 KB 50% 12 5.3-5.9 W 1.35 V 130 nm Al
C3 Ezra-T (C5N) 800-1000 MHz 100-133 MHz 128 KB 64 KB 50% 12 5.3-11.8 W 1.35 V 130 nm Al

C3, C7[edit]

Marketing
name
Core Frequency Front-side bus L1 cache L2 cache FPU
speed
Pipeline
stages
Typical power Voltage Process
C3, Eden ESP, Eden-N Nehemiah (C5XL) 800-1400 MHz 133 MHz 128 KB 64 KB 100% 16 15-19 W 1.25 or 1.4-1.45 V 130 nm Cu
C3 Nehemiah+ (C5P) 1-1.4 GHz 133 MHz 128 KB 64 KB 100% 16 11-12 W 1.25 V 130 nm Cu
C7, C7-D, C7-M, Eden, Eden ULV Esther (C5J) 0.4-2.0 GHz 400-533 MT/s 128 KB 128 KB 100% 16 12-20 W 0.9-1.1(?) V 90 nm SOI
Series Model Core Frequency
[MHz]
Front-side bus
[MHz]
Year Process
[nm]
Package size
[mm2]
Power
[W]
L2 cache
[K]
L1 I/D cache
[K]
Performance
[SPEC2000]
Eden Eden ESP Samuel 2 300–600 66/100/133 2001 150 35×35 2.5–6 64 64/64 Un­known
Eden ESP Nehemiah 667–1000 133/200 2003–2004 130 35×35 6–7 64 64/64 Un­known
Eden-N Nehemiah 533–1000 133 2003 130 15×15 2.5–7 64 64/64 Un­known
Eden Esther 400–1500 400–800 2006–2007 90 30 <7.5 128 32/32 Un­known
Eden X2 Un­known 800 Un­known 2011 40 11×6 Un­known Un­known Un­known Un­known
C3 C3 Samuel 2 667–800 100–133 2001 150 Un­known 13 64 64/64 Un­known
C3 Ezra 800–1000 100–133 2002 130 Un­known 8.3–10 64 64/64 Un­known
C3 Nehemiah 1000–1400 133–200 2003 130 35×35 15–21 64 64/64 Un­known
C3-M Nehemiah 1000–1400 133–200 2003 130 35×35 11–19 64 64/64 Un­known
C7 C7-D Esther 1500–1800 400 2006 90 21×21 20–25 128 16/16 Un­known
C7-M Esther 1000–2000 400 2005 90 21×21 12–20 128 16/16 Un­known
C7 Esther 1500–2000 800 2007 90 21×21 12–20 128 16/16 Un­known

Nano[edit]

Series Model Core Frequency
[MHz]
Front-side bus
[MHz]
Year Process
[nm]
Package size
[mm2]
Power
[W]
L2 cache
[K]
L1 I/D cache
[K]
Performance
[SPEC2000]
QuadCore QuadCore Isaiah 1000-1460 1066 2011 40 21×21 27.5 4× 1024[5] 4× 64/64 30.1/24.1 rate[6]

CHA[7][8][9][edit]

  • Currently in development. Details listed below are subject to change,
  • 8 cores + "NCORE" neural processor for AI acceleration.
  • supports: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES AVX AVX2 FMA3 SHA AVX512 AVX512F AVX512CD AVX512BW AVX512DQ AVX512VL AVX512IFMA AVX512VBMI.
Marketing
name
Code name Core Number of cores Frequency Microarchitecture L1 cache L2 cache L3 cache Announced Expected Release Process Socket Type Pipeline stages PCIe Lanes
unknown CHA CNS 8 2.5 GHz CNS[10] 32 KiB 256 KiB 16 MB 2019 2H 2020[11] 16 nm LGA 20-22 44[12]

See also[edit]

References[edit]

  1. ^ "IA-32 implementation: VIA Cyrix III". sandpile.org. Archived from the original on 2007-07-09. Retrieved 2007-07-23. CS1 maint: discouraged parameter (link)
  2. ^ "IA-32 implementation: VIA C3". sandpile.org. Archived from the original on 2007-07-17. Retrieved 2007-07-23. CS1 maint: discouraged parameter (link)
  3. ^ "IA-32 implementation: VIA C7". sandpile.org. Archived from the original on 2007-06-30. Retrieved 2007-07-23. CS1 maint: discouraged parameter (link)
  4. ^ "VIA Nano X2 SPEC2000 ratio and rate scores". Via.com. Archived from the original on 7 February 2014. Retrieved 3 February 2014. CS1 maint: discouraged parameter (link)
  5. ^ "VIA QuadCore Processor". Via.com. Retrieved 2014-02-03. CS1 maint: discouraged parameter (link)
  6. ^ "VIA Nano X2 Whitepaper" (PDF). Via.com. Archived from the original (PDF) on 27 May 2012. Retrieved 3 February 2014. CS1 maint: discouraged parameter (link)
  7. ^ Nov 18th, btarunr; Discuss, 2019 22:10. "VIA CenTaur Develops a Multi-core x86 Processor for Enterprise with in-built AI Hardware". TechPowerUp. Retrieved 2020-07-28.CS1 maint: numeric names: authors list (link)
  8. ^ Feb 18th, btarunr; Discuss, 2020 06:36. "VIA CenTaur CHA NCORE AI CPU Pictured, a Socketed LGA Package". TechPowerUp. Retrieved 2020-07-28.CS1 maint: numeric names: authors list (link)
  9. ^ "CHA - Microarchitectures - Centaur Technology - WikiChip". en.wikichip.org. Retrieved 2020-07-28.
  10. ^ "VIA x86 AI processor architecture, performance announcement: comparable to Intel 32 core". Small Tech News. December 11, 2019.
  11. ^ Dec 9th, btarunr; Discuss, 2019 18:25. "Centaur Releases In-Depth Analysis from The Linley Group for its NCORE-Equipped x86 Processor". TechPowerUp. Retrieved 2020-08-30.CS1 maint: numeric names: authors list (link)
  12. ^ "World's First High-Performancex86 SoCwithIntegrated AI Coprocessor" (PDF). centtech. p. 4.

External links[edit]