Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.
Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In
flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.
Through-hole packages [ edit ]
Through-hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.
Three 14-pin (DIP14) plastic dual in-line packages containing IC chips.
Single in-line package
Dual in-line package 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) or 0.6 in (15.24 mm) apart.
QIP Quadruple in-line package
Like DIP but with staggered (zig-zag) pins.
DIP Standard DIP with 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) apart.
DIP Non-standard DIP with smaller 0.07 in (1.78 mm) pin spacing.
ZIP Zig-zag in-line package
Surface mount [ edit ]
Ceramic column-grid array (CGA)
Lead-less lead-frame package
A package with metric pin distribution (0.5–0.8 mm pitch)
LGA Land grid array
LTCC Low-temperature co-fired ceramic
MCM Multi-chip module
Micro surface-mount device extended technology
Chip carrier [ edit ]
chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.
Bump chip carrier
Ceramic lead-less chip carrier
Lead-less chip carrier
 Contacts are recessed vertically.
Leaded chip carrier
Leaded ceramic-chip carrier
Dual lead-less chip carrier (ceramic)
Plastic leaded chip carrier
  -
Pin grid arrays [ edit ]
Organic pin-grid array
Flip-chip pin-grid array
Pin array cartridge
Also known as PPGA
Ceramic pin-grid array
Flat packages [ edit ]
Flat-pack Earliest version metal/ceramic packaging with flat leads
Ceramic quad flat-pack
  Similar to PQFP
Bumpered quad flat-pack
Exposed thin quad flat-package
Power quad flat-pack
No-leads, with exposed die-pad[s] for heatsinking
PQFP Plastic quad flat-package
  -
Low-profile quad flat-package
Quad flat no-leads package Also called as micro lead frame ( MLF). 
Quad flat package   -
Metric quad flat-pack
QFP with metric pin distribution
Heat-sink very-thin quad flat-pack, no-leads
Thin quad flat-pack
  -
Very-thin quad flat-pack
Thin quad flat, no-lead
Very-thin quad flat, no-lead
Very-very-thin quad flat, no-lead
Ultra-thin quad flat-pack, no-lead
Optical dual flat, no-lead
IC packaged in transparent packaging used in optical sensor
Small outline packages [ edit ]
SOP Small-outline package
Ceramic small-outline package
Thermally-enhanced small-outline package
mini-SOIC Mini small-outline integrated circuit
Mini small-outline package
Plastic small-outline package
Plastic small-outline no-lead package
Quarter-size small-outline package
The pin spacing are width of 0.635 mm.
SOIC Small-outline integrated circuit
Also known as SOIC NARROW and SOIC WIDE
SOJ Small-outline J-leaded package
SSOP Shrink small-outline package
TSOP Thin small-outline package
TSSOP Thin shrink small-outline package
Thin very-small-outline package
Similar to a SOIC. (A Maxim trademark example)
Very-very-thin small-outline no-lead package
Chip-scale packages [ edit ]
Example WL-CSP devices sitting on the face of a
device is shown for comparison.
Beam lead technology
Bare silicon chip, an early chip-scale package
CSP Chip-scale package
Package size is no more than 1.2× the size of the silicon chip 
True chip-size package
Package is same size as silicon
True die-size package
Same as TCSP
Wafer-level chip-scale package
Chip-size package (CSP) developed by National Semiconductor
Bare silicon chip, that is usually an integrated circuit, is supplied without a package.
Variation of COB, where a chip is mounted directly to a flex circuit.
Variation of COB, where a chip is mounted directly to a piece of glass - typically an LCD.
Ball grid array [ edit ]
Ball Grid Array
BGA uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB. 
FBGA Fine-pitch ball-grid array
A square or rectangular array of solder balls on one surface
Low-profile ball-grid array
Also known as laminate ball-grid array
Thermally-enhanced plastic ball-grid array
Ceramic ball-grid array
Organic ball-grid array
Thin fine-pitch ball-grid array
Plastic ball-grid array
Mold array process - ball-grid array
Micro (μ) chip-scale package
Similar to a BGA (A Maxim trademark example)
Micro ball-grid array
Ball spacing less than 1 mm
Low-profile fine-pitch ball-grid array
Thin ball-grid array
Super ball-grid array
 Above 500 balls
Ultra-fine ball-grid array
Transistor, diode, small-pin-count IC packages [ edit ]
MELF: Metal electrode leadless face (usually for resistors and diodes) SOD: Small-outline diode.
Small-outline transistor (also SOT-23, SOT-223, SOT-323). TO-XX: wide range of small pin count packages often used for discrete parts like transistors or diodes.
TO-3: Panel-mount with leads
TO-5: Metal can package with radial leads
TO-18: Metal can package with radial leads TO-39
TO-66: Similar shape to the TO-3 but smaller
TO-92: Plastic-encapsulated package with three leads TO-99
TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads TO-226
TO-247: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink 
TO-251: Also called IPAK: SMT package similar to the DPAK but with longer leads for SMT or TH mounting 
TO-252: (also called SOT428, DPAK):  SMT package similar to the DPAK but smaller 
TO-262: Also called I2PAK: SMT package similar to the D2PAK but with longer leads for SMT or TH mounting 
TO-263: Also called D2PAK: SMT package similar to the TO-220 without the extended tab and mounting hole  TO-274: Also called Super-247: SMT package similar to the TO-247 without the mounting hole 
Dimension reference [ edit ]
Surface-mount [ edit ]
Clearance between IC body and PCB
Total carrier length
W Lead width
L Lead length
Through-hole [ edit ]
Clearance between IC body and board
Total carrier length
W Lead width
L Lead length
B IC body width
L Lead-to-lead width
Package dimensions [ edit ]
All measurements below are given in
. To convert mm to mm mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).
Clearance between package body and
Height of package from pin tip to top of package.
Thickness of pin.
Length of package body only.
W Pin width.
L Pin length from package to pin tip.
Pin pitch (distance between conductors to the PCB).
B Width of the package body only.
L Length from pin tip to pin tip on the opposite side.
Dual row [ edit ]
Dual inline package
Lead-frame chip-scale package
Mini small-outline package
Small-outline integrated circuit
Shrink small-outline package
Thin dual flat no-lead
Thin small-outline package
Thin shrink small-outline package
Micro small-outline package
US8  Y
Quad rows [ edit ]
Plastic leaded chip-carrier
Ceramic leadless chip-carrier
Low-profile Quad Flat Package
Thin quad flat-package
Thin quad flat no-lead
mm 0.65 mm
mm 0.10 mm
Multi-chip packages [ edit ]
A variety of techniques for interconnecting several chips within a single package have been proposed and researched:
See also [ edit ]
References [ edit ]
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"CPU Collection Museum - Chip Package Information". The CPU Shack . Retrieved . 2011-12-15
"Archived copy" (PDF). Archived from the original (PDF) on 2011-08-15 . Retrieved . 2011-02-03 CS1 maint: Archived copy as title ( link)
^ a b c d e f g h i j k l m n o p q r s t u v w x y z aa ab ac ad ae af ag ah ai aj ak al am
"Integrated Circuit, IC Package Types; SOIC. Surface Mount Device Package". Interfacebus.com . Retrieved . 2011-12-15
"National Semiconductor CERPACK Package Products". National.com. Archived from the original on 2012-02-18 . Retrieved . 2011-12-15
"National Semiconductor CQGP Package Products". National.com. Archived from the original on 2007-10-21 . Retrieved . 2011-12-15
"National's LLP Package". National.com. Archived from the original on 2011-02-13 . Retrieved . 2011-12-15
"LTCC Low Temperature Co-fired Ceramic". Minicaps.com . Retrieved . 2011-12-15
Frye, R.C.; Gabara, T.J.; Tai, K.L.; Fischer, W.C.; Knauer, S.C. (1993). "Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs". IEEE Xplore - Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs. Ieeexplore.ieee.org. pp. 464–467. doi: 10.1109/ASIC.1993.410760. ISBN 978-0-7803-1375-0 . Retrieved . 2011-12-15
"National Semiconductor Launches New Generation of Ultra-Miniature, High Pin-Count Integrated Circuit Packages". National.com. Archived from the original on 2012-02-18 . Retrieved . 2011-12-15
Meyers, Michael; Jernigan, Scott (2004). . Mike Meyers' A+ Guide to PC Hardware The McGraw-Hill Companies. ISBN 978-0-07-223119-9.
 Archived August 18, 2011, at the Wayback Machine
"Press Releases - Motorola Mobility, Inc". Motorola.com . Retrieved . 2011-12-15
"Xilinx new CPLDs with two I/O banks". Eetasia.com. 2004-12-08 . Retrieved . 2011-12-15
"Packages". Chelseatech.com. 2010-11-15 . Retrieved . 2011-12-15
"Archived copy". Archived from the original on 2008-11-20 . Retrieved . 2009-10-24 CS1 maint: Archived copy as title ( link)
"CSP - Chip Scale Package". Siliconfareast.com . Retrieved . 2011-12-15
^ a b
"Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications - Maxim". Maxim-ic.com. 2007-04-18 . Retrieved . 2011-12-15
^ a b
"Chip Scale Review Online". Chipscalereview.com . Retrieved . 2011-12-15
"Packaging Technology | National Semiconductor – Package Drawings, Part Marking, Package Codes, LLP, micro SMD, Micro-Array". National.com. Archived from the original on 2010-08-01 . Retrieved . 2011-12-15
^ a b c d e f g
"Fairchild's TinyLogic family overview" (PDF). March 22, 2013. Archived from the original (PDF) on January 8, 2015.
, 2004, archived from Proximity Communication - the Technology the original on 2009-07-18
External links [ edit ]