In digital circuits, a logic level is one of a finite number of states that a digital signal can inhabit. Logic levels are usually represented by the voltage difference between the signal and ground, although other standards exist. The range of voltage levels that represent each state depends on the logic family being used.
In binary logic the two levels are logical high and logical low, which generally correspond to binary numbers 1 and 0 respectively. Signals with one of these two levels can be used in boolean algebra for digital circuit design or analysis.
The use of either the higher or the lower voltage level to represent either logic state is arbitrary. The two options are active high and active low. Active-high and active-low states can be mixed at will: for example, a read only memory integrated circuit may have a chip-select signal that is active-low, but the data and address bits are conventionally active-high. Occasionally a logic design is simplified by inverting the choice of active level (see De Morgan's laws).
|Logic level||Active-high signal||Active-low signal|
The name of an active-low signal is historically written with a bar above it to distinguish it from an active-high signal. For example, the name Q, read "Q bar" or "Q not", represents an active-low signal. The conventions commonly used are:
- a bar above (Q)
- a leading slash (/Q)
- a lower-case n prefix or suffix (nQ or Q_n)
- a trailing # (Q#), or
- an "_B" or "_L" suffix (Q_B or Q_L).
Many control signals in electronics are active-low signals  (usually reset lines, chip-select lines and so on). Logic families such as TTL can sink more current than they can source, so fanout and noise immunity increase. It also allows for wired-OR logic if the logic gates are open-collector/open-drain with a pull-up resistor. Examples of this are the I²C bus and the Controller Area Network (CAN),and the PCI Local Bus.
Some signals have a meaning in both states and notation may indicate such. For example, it is common to have a read/write line designated R/W, indicating that the signal is high in case of a read and low in case of a write.
Logic voltage levels
The two logical states are usually represented by two different voltages, but two different currents are used in some logic signaling, like digital current loop interface and current-mode logic. High and low thresholds are specified for each logic family. When below the low threshold, the signal is "low". When above the high threshold, the signal is "high". Intermediate levels are undefined, resulting in highly implementation-specific circuit behavior.
It is usual to allow some tolerance in the voltage levels used; for example, 0 to 2 volts might represent logic 0, and 3 to 5 volts logic 1. A voltage of 2 to 3 volts would be invalid and occur only in a fault condition or during a logic level transition. However, few logic circuits can detect such a condition, and most devices will interpret the signal simply as high or low in an undefined or device-specific manner. Some logic devices incorporate Schmitt trigger inputs, whose behavior is much better defined in the threshold region and have increased resilience to small variations in the input voltage. The problem of the circuit designer is to avoid circumstances that produce intermediate levels, so that the circuit behaves predictably.
|Technology||L voltage||H voltage||Notes|
|CMOS||0 V to 1/3 VDD||2/3 VDD to VDD||VDD = supply voltage|
|TTL||0 V to 0.8 V||2 V to VCC||VCC = 5 V ±10%|
Nearly all digital circuits use a consistent logic level for all internal signals. That level, however, varies from one system to another. Interconnecting any two logic families often required special techniques such as additional pull-up resistors or purpose-built interface circuits known as level shifters. A level shifter connects one digital circuit that uses one logic level to another digital circuit that uses another logic level. Often two level shifters are used, one at each system: A line driver converts from internal logic levels to standard interface line levels; a line receiver converts from interface levels to internal voltage levels.
For example, TTL levels are different from those of CMOS. Generally, a TTL output does not rise high enough to be reliably recognized as a logic 1 by a CMOS input, especially if it is only connected to a high-input-impedance CMOS input that does not source significant current. This problem was solved by the invention of the 74HCT family of devices that uses CMOS technology but TTL input logic levels. These devices only work with a 5 V power supply.
|Supply voltage||Technology||Logic families (examples)||Reference|
|5V, 10V, 15V||Metal CMOS||4000, 74C|||
|5V||TTL||7400, 74S, 74LS, 74ALS, 74F, 74H|||
|5V||CMOS (TTL I/O)||74HCT, 74AHCT, 74ACT|||
|3.3V, 5V||CMOS||74HC, 74AHC, 74AC|||
|3.3V||LVCMOS||74LVC, 74AUP, 74AXC, 74AXP|||
|2.5V||LVCMOS||74LVC, 74AUP, 74AUC, 74AXC, 74AXP|||
|1.8V||LVCMOS||74LVC, 74AUP, 74AUC, 74AXC, 74AXP|||
|1.5V||LVCMOS||74AUP, 74AUC, 74AXC, 74AXP|||
|1.2V||LVCMOS||74AUP, 74AUC, 74AXC, 74AXP|||
In three-state logic, an output device can be in one of three possible states: 0, 1, or Z, with the last meaning high impedance. This is not a logic level, but means that the output is not controlling the state of the connected circuit.
4-level logic adds a fourth state, X ("don't care"), meaning the value of the signal is unimportant and undefined. It means that an input is undefined, or an output signal may be chosen for implementation convenience (see Karnaugh map § Don't cares).
In solid-state storage devices, a multi-level cell stores data using multiple voltages. Storing n bits in one cell requires the device to reliably distinguish 2n distinct voltage levels.
- "Coding Style Guidelines" (PDF). Xilinx. Retrieved 2017-08-17.
- Balch, Mark (2003). Complete Digital Design: A Comprehensive Guide To Digital Electronics And Computer System Architecture. McGraw-Hill Professional. p. 430. ISBN 978-0-07-140927-8.
- "Logic signal voltage levels". All About Circuits. Retrieved 2015-03-29.
- "HEF4000B Family Specifications" (PDF). Philips Semiconductors. January 1995. Archived from the original (PDF) on March 4, 2016.
Parametric limits are guaranteed for VDD of 5V, 10V, and 15V.
- "AppNote 319 - Comparison of MM74HC to 74LS, 74S and 74ALS Logic" (PDF). Fairchild Semiconductor. June 1983. Archived (PDF) from the original on October 24, 2021.
- "AHC/AHCT Designer's Guide" (PDF). Texas Instruments. September 1998. Archived (PDF) from the original on April 13, 2018.
Technical Comparison of AHC / HC / AC (CMOS I/O) and AHCT / HCT / ACT (TTL I/O) Logic Families
- "Little Logic Guide" (PDF). Texas Instruments. 2018. Archived (PDF) from the original on April 3, 2021.
Logic Voltage Graph (page4)