Memory ordering

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Memory ordering describes the order of accesses to computer memory by a CPU. The term can refer either to the memory ordering generated by the compiler during compile time, or to the memory ordering generated by a CPU during runtime.

In modern microprocessors, memory ordering characterizes the CPUs ability to reorder memory operations - it is a type of out-of-order execution. Memory reordering can be used to fully utilize the bus-bandwidth of different types of memory such as caches and memory banks.

On most modern uniprocessors memory operations are not executed in the order specified by the program code. In single threaded programs all operations appear to have been executed in the order specified, with all out-of-order execution hidden to the programmer – however in multi-threaded environments (or when interfacing with other hardware via memory buses) this can lead to problems. To avoid problems memory barriers can be used in these cases.

Compile-time memory ordering[edit]

The compiler has some freedom to sort the order of operations during compile time. However this can lead to problems if the order of memory accesses is of importance.

Compile-time memory barrier implementation[edit]

These barriers prevent a compiler from reordering instructions during compile time – they do not prevent reordering by CPU during runtime.

  • The GNU inline assembler statement
asm volatile("" ::: "memory");

or even

__asm__ __volatile__ ("" ::: "memory");

forbids GCC compiler to reorder read and write commands around it.[1]

  • The C11/C++11 command

forbids the compiler to reorder read and write commands around it.[2]




Runtime memory ordering[edit]

In symmetric multiprocessing (SMP) microprocessor systems[edit]

There are several memory-consistency models for SMP systems:

  • Sequential consistency (all reads and all writes are in-order)
  • Relaxed consistency (some types of reordering are allowed)
    • Loads can be reordered after loads (for better working of cache coherency, better scaling)
    • Loads can be reordered after stores
    • Stores can be reordered after stores
    • Stores can be reordered after loads
  • Weak consistency (reads and writes are arbitrarily reordered, limited only by explicit memory barriers)

On some CPUs

  • Atomic operations can be reordered with loads and stores.
  • There can be incoherent instruction cache pipeline, which prevents self-modifying code from being executed without special instruction cache flush/reload instructions.
  • Dependent loads can be reordered (this is unique for Alpha). If the processor fetches a pointer to some data after this reordering, it might not fetch the data itself but use stale data which it has already cached and not yet invalidated. Allowing this relaxation makes cache hardware simpler and faster but leads to the requirement of memory barriers for readers and writers.[6]
Memory ordering in some architectures[7][8]
Type Alpha ARMv7 PA-RISC POWER SPARC x86 [a] AMD64 IA-64 z/Architecture
Loads reordered after loads Y Y Y Y Y Y
Loads reordered after stores Y Y Y Y Y Y
Stores reordered after stores Y Y Y Y Y Y Y
Stores reordered after loads Y Y Y Y Y Y Y Y Y Y Y
Atomic reordered with loads Y Y Y Y Y
Atomic reordered with stores Y Y Y Y Y Y
Dependent loads reordered Y
Incoherent instruction cache pipeline Y Y Y Y Y Y Y Y
  1. ^ This column indicates the behaviour of the vast majority of x86 processors. Some rare specialised x86 processors (IDT WinChip manufactured around 1998) may have weaker 'oostore' memory ordering.[9]

SPARC memory ordering modes:

Total store order (default)
Relaxed-memory order (not supported on recent CPUs)
Partial store order (not supported on recent CPUs)

Hardware memory barrier implementation[edit]

Many architectures with SMP support have special hardware instruction for flushing reads and writes during runtime.

lfence (asm), void _mm_lfence(void)
sfence (asm), void _mm_sfence(void)[10]
mfence (asm), void _mm_mfence(void)[11]
sync (asm)
sync (asm)
mf (asm)
dcs (asm)
dmb (asm)
dsb (asm)
isb (asm)

Compiler support for hardware memory barriers[edit]

Some compilers support builtins that emit hardware memory barrier instructions:

See also[edit]


  1. ^ GCC compiler-gcc.h Archived 2011-07-24 at the Wayback Machine
  2. ^ [1]
  3. ^ ECC compiler-intel.h Archived 2011-07-24 at the Wayback Machine
  4. ^ Intel(R) C++ Compiler Intrinsics Reference

    Creates a barrier across which the compiler will not schedule any data access instruction. The compiler may allocate local data in registers across a memory barrier, but not global data.

  5. ^ Visual C++ Language Reference _ReadWriteBarrier
  6. ^ Reordering on an Alpha processor by Kourosh Gharachorloo
  7. ^ Memory Ordering in Modern Microprocessors by Paul McKenney
  8. ^ Memory Barriers: a Hardware View for Software Hackers, Figure 5 on Page 16
  9. ^ Table 1. Summary of Memory Ordering, from "Memory Ordering in Modern Microprocessors, Part I"
  10. ^ SFENCE — Store Fence
  11. ^ MFENCE — Memory Fence
  12. ^ Data Memory Barrier, Data Synchronization Barrier, and Instruction Synchronization Barrier.
  13. ^ Atomic Builtins
  14. ^
  15. ^ MemoryBarrier macro
  16. ^ Handling Memory Ordering in Multithreaded Applications with Oracle Solaris Studio 12 Update 2: Part 2, Memory Barriers and Memory Fence [2]

Further reading[edit]