Memory timings or RAM timings describe the performance of synchronous dynamic random-access memory (SDRAM) using four parameters: CL, TRCD, TRP, and TRAS in units of clock cycles; they are commonly written as four numbers separated with dashes, e.g. 7-8-8-24. The fourth (tRAS) is often omitted, or a fifth, the Command rate, sometimes added (normally 2T or 1T, also written 2N, 1N). These parameters specify the latencies (time delays) that affect speed of random access memory. Lower numbers usually imply faster performance. What determines absolute system performance is actual latency time, usually measured in nanoseconds.
When translating memory timings into actual latency, it is important to note that they are in units of clock cycles, which for double data rate memory is half the speed of the commonly quoted transfer rate. Without knowing the clock cycle times, it is impossible to state if one set of numbers is "faster" than another.
For example, DDR3-2000 memory has a 1000 MHz clock frequency, which yields a 1 ns clock cycle. With this 1 ns clock, CL=7 gives an absolute latency of 7 ns. Faster DDR3-2666 (with a 1333 MHz clock, or 0.75 ns per cycle), may have a larger CL=9, but that still results in a shorter absolute latency of 6.75 ns.
Modern DIMMs include a Serial Presence Detect (SPD) ROM chip that contains recommended memory timings for automatic configuration. The BIOS on a PC may allow the user to make adjustments in an effort to increase performance (with possible risk of decreased stability) or, in some cases, to increase stability (by using suggested timings).
Note: Memory bandwidth measures the throughput of memory, and is generally limited by the transfer rate, not latency. By interleaving access to SDRAM's multiple internal banks, it is possible to transfer data continuously at the peak transfer rate. It is possible for increased bandwidth to come at a cost in latency. In particular, each successive generation of DDR memory has higher transfer rates but the absolute latency does not change significantly, and especially when first appearing on the market, the new generation generally has longer latency that the previous one.
Increasing memory bandwidth, even while increasing memory latency, can improve the performance of a computer system with multiple processors, and also systems with processors that have multiple execution threads. Higher bandwidth will also boost performance of integrated graphics that have no dedicated video memory.
|CAS latency||CL||The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a maximum, but an exact number that must be agreed on between the memory controller and the memory.|
|Row Address to Column Address Delay||TRCD||The minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL.|
|Row Precharge Time||TRP||The minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.|
|Row Active Time||TRAS||The minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL.|