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|Max. CPU clock rate||12.5 MHz to 33 MHz|
|Data width||32 bits|
|Address width||32 bits|
|L1 cache||256 byte instruction cache: 578 |
|Architecture and classification|
|Instruction set||Motorola 68000 series|
|Products, models, variants|
The Motorola 68020 ("sixty-eight-oh-twenty", "sixty-eight-oh-two-oh" or "six-eight-oh-two-oh") is a 32-bit microprocessor from Motorola, released in 1984. A lower cost version was also made available, known as the 68EC020. In keeping with naming practices common to Motorola designs, the 68020 is usually referred to as the "020", pronounced "oh-two-oh" or "oh-twenty".
The 68020 has 32-bit internal and external data and address buses, compared to the early 680x0 models with 16-bit data and 24-bit address buses. The 68020's ALU is also natively 32-bit, so can perform 32-bit operations in one clock cycle, whereas the 68000 took a minimum of two clock cycles due to its 16-bit ALU. Newer packaging methods allowed the '020 to feature more external pins without the large size that the earlier dual in-line package method required. The 68EC020 lowered cost through a 24-bit address bus. The 68020 was produced at speeds ranging from 12 MHz to 33 MHz.
Improvements over the 68010
The 68020 has a 32-bit arithmetic logic unit (ALU), 32-bit external data and address buses. It adds extra instructions and additional addressing modes. The 68020 (and 68030) has a proper three-stage pipeline. Though the 68010 had a "loop mode", which sped loops through what was effectively a tiny instruction cache, it held only two short instructions and was thus little used. The 68020 replaced this with a proper instruction cache of 256 bytes, the first 68k series processor to feature true on-chip cache memory.
The previous 68000 and 68010 processors could only access word (16-bit) and long word (32-bit) data in memory if it were word-aligned (located at an even address). The 68020 has no alignment restrictions on data access. Naturally, unaligned accesses are slower than aligned accesses because they required an extra memory access.
The 68020 has a small 256-byte direct-mapped instruction cache, arranged as 64 four-byte entries. Although small, it still made a significant difference in the performance of many applications. The resulting decrease in bus traffic was particularly important in systems relying heavily on DMA.
The 68020 has a coprocessor interface supporting up to eight coprocessors. The main CPU recognizes "F-line" instructions (with the four most significant opcode bits all one), and uses special bus cycles to interact with a coprocessor to execute these instructions. Two types of coprocessors were defined: floating point units (MC68881 or MC68882 FPUs) and the paged memory management unit (MC68851 PMMU). Only one PMMU can be used with a CPU. In principle, multiple FPUs could be used with a CPU, but it was not commonly done. The coprocessor interface is asynchronous, so it is possible to run the coprocessors at a different clock rate than the CPU.
Multiprocessing support is implemented externally by the use of a RMC pin to indicate an indivisible read-modify-write cycle in progress. All other processors have to hold off memory accesses until the cycle is complete. Software support for multiprocessing includes the TAS, CAS and CAS2 instructions.
In a multiprocessor system, coprocessors could not be shared between CPUs. To avoid problems with returns from coprocessor, bus error, and address error exceptions, it was generally necessary in a multiprocessor system for all CPUs to be the same model, and for all FPUs to be the same model as well.
The new instructions include some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.
While the 68000 had a 'supervisor mode', it did not meet the Popek and Goldberg virtualization requirements due to the single instruction 'MOVE from SR' being unprivileged but sensitive. Under the 68010 and later, this was made privileged, to better support virtualization software.
With full 32-bit internal and external address buses, the address registers (A0 through A7) could utilize their full 32-bit width, and were capable of addressing the entire 4 GB address space.
The larger effective widths of the address registers presented some problem for earlier software that was not considered "32-bit clean". Some programs used the high 8 bits (bits 24-31) of addresses to contain various flag bits, with the understanding that the earlier 680x0 CPUs would safely ignore these high bits. Such software had to be rewritten to adjust to the larger physical address space available to the 68020 and later CPUs.
The 68020 was used in the Apple Macintosh II and Macintosh LC personal computers, Sun-3 workstations, Amiga 1200 (68EC020 variant), the Hewlett-Packard 8711 Series Network Analyzers, HP 9000/320, HP 9000/330, and the Alpha Microsystems AM-2000. The 68020 was an alternative upgrade to the Sinclair QL's 68008 in the Super Gold Card interface by Miracle Systems.
A number of digital oscilloscopes from the mid-80s to the late-90s used the 68020, including the LeCroy 9300 Series (higher end models including "C" suffix models used the more powerful 68EC030; the 9300 models with a 68020 processor can be upgraded to the 68EC030 with a change of the CPU board) and the earlier LeCroy 9400 series (all models excluding the 9400/9400A which used the 68000), along with certain Tektronix TDS Series models. The HP 54520, 54522, 54540 and 54542 also use the 68020, together with a 68882 FPU.
It is also the processor used on TGV trains to decode signalling information sent to the trains through the rails. It is used in the flight control and radar systems of the Eurofighter Typhoon combat aircraft.
The 68EC020 is a lower cost version of the Motorola 68020. The main difference is that the 68EC020 only has a 24-bit address bus, rather than the 32-bit address bus of the full 68020, and thus is only able to address 16 MB of memory.
The Amiga 1200 computer and the Amiga CD32 game console use the cost-reduced 68EC020; the Namco System 22, Taito F3 and Konami GX arcade boards also used this processor. The Atari Jaguar II prototype featured this to replace the 68000 of the original Atari Jaguar console.
It also found use in laser printers. Apple used it in the LaserWriter IIɴᴛx. Kodak used it in the Ektaplus 7016PS, and Dataproducts used it in the LZR 1260.
In 2014, Rochester Electronics re-established manufacturing capability for the 68020 microprocessor and it is still available today.
|Formal name||MC68020: 577|
|CPU clock rate||12.5, 16.67, 20, 25, 33 MHz (minimum 8 MHz, no on-chip clock generation): 577|
|Voltage supply||5 V|
|Maximum power||1.75 W: 577|
|Production process||HCMOS, 3/8" silicon piece: 577|
|Chip carrier||PGA 169 (114 pins used) 34.16 mm × 34.16 mm: 577 (53 °C/W without heatsink)|
|Address bus||32-bit (4 GB directly linear addressable): 578 |
[68EC020] 24-bit (16 MB addressable)
|Instruction set||101 CISC instructions|
|Cache||256 byte instruction cache: 578 |
|Branch handling||Branch prediction:
|Performance||10 MIPS @ 33 MHz|
- Rafiquzzaman, M. (2005). Fundamentals of Digital Logic and Microcomputer Design. John Wiley & Sons. p. 577-578. ISBN 978-0471733492.
- "MC68020 MCEC68020 Microprocessors User's Manual" (PDF). Freescale Semiconductor. 1992. M68020UM/AD REV.2. Archived from the original (PDF) on March 4, 2016.
- Hekimoglu, M. Kadri (March 1991). "Video-Text Processing By Using Motorola 68020 CPU And Its Environment" (PDF). MC68020 Signal Description, Appendix A, p. 84. Retrieved 2020-01-06.
- "5.3.3 Read-Modify-Write Cycle". MC68020/MC68EC020 Microprocessors User's Manual UM Rev. 1.0 (PDF). Freescale Semiconductor. 1995.
- LeCroy 1996 Test & Measurement Product Catalog, 9300 Series Upgrade Path, p. 66
- LeCroy 1998 Test & Measurement Product Catalog, 9300 Series Hardware Options, Mega Waveform Processing, pp. 87–88
- LeCroy 1996 Test & Measurement Product Catalog, 9300 Series Hardware Options, Mega Waveform Processing, pp. 66-67
- LeCroy 9410 Digital Oscilloscope Service Manual, 9410 Hardware Overview, Section 2.1, December 1991
- LeCroy 9424 Digital Oscilloscope Service Manual, 9424 Hardware Overview, Section 2.1, May 1993
- LeCroy 9450 Digital Oscilloscope Service Manual, 9450 Hardware Overview, October 1990
- LeCroy 9450A Digital Oscilloscope Service Manual, 9450 Hardware Overview, December 1991
- LeCroy 9400/9400A Digital Oscilloscope Service Manual, Section 126.96.36.199 Microprocessor, August 1990
- Tektronix TDS684A, TDS744A, & TDS784A Digitizing Oscilloscope Service Manual, 070-8992-03, January 1995
- Hewlett Packard 54520 and 54540 Series Oscilloscope Service Guide (54542-97015), Chapter 8, Main Assembly Theory, April 1994
- Dandamudi, S. P. (2004). Guide to RISC Processors. p. 29. ISBN 0-387-21017-2.
- "MC68020: 32-Bit Microprocessor". NXP Semiconductors.
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