Multi-project wafer service

From Wikipedia, the free encyclopedia

Multi-project chip (MPC), and multi-project wafer (MPW) semiconductor manufacturing arrangements allow customers to share tooling (like mask) and microelectronics wafer fabrication cost between several designs or projects.

MPC consisting of five CMOS IC designs and few test N- and PMOS transistors for manufacturing acceptance

With the MPC arrangement, one chip is a combination of several designs and this combined chip is then repeated all over the wafer during the manufacturing. MPC arrangement produces typically roughly equal number of chip designs per wafer.

A wafer consisting of MPC designs all over the wafer and five process control monitor (PCM) designs for ensuring good quality of the processing

With the MPW arrangement, different chip designs are aggregated on a wafer, with perhaps a different number of designs/projects per wafer. This is made possible with novel mask making and exposure systems in photolithography during IC manufacturing. MPW builds upon the older MPC procedures and enables more effective support for different phases and needs of manufacturing volumes of different designs/projects. MPW arrangement support education, research of new circuit architectures and structures, prototyping and even small volume production.[1][2]

A multi-project wafer consisting of several different unequal number of designs/projects.

Worldwide, several MPW services are available from companies, semiconductor foundries and from government-supported institutions. Originally both MPC and MPW arrangements were introduced for integrated circuit (IC) education and research; some MPC/MPW services/gateways are aimed for non-commercial use only. Currently MPC/MPW services are effectively used for system on a chip integration. Selecting the right service platform at the prototyping phase ensures gradual scaling up production via MPW services taking into account the rules of the selected service.

MPC/MPW arrangements have also been applied to microelectromechanical systems (MEMS),[3] integrated photonics[4] like silicon photonics fabrication, flexible electronics, microfluidics and even chiplets.[5][6]

A refinement of MPW is multi-layer mask (MLM) arrangement, where a limited number of masks (e.g. 4) are changed during manufacturing at exposure phase. The rest of the masks are the same from the chip to chip on the whole wafer.[7] MLM approach is well suited for several specific cases:

  • Large (even possibly part or whole wafer) designs like detectors, where by using few mask layers it is possible to form functional devices
  • Making different versions of one design/project like for different performance or standards of one design

Typically MLM approach is used for one wafer batch (consisting of several wafers depending on the fabrication line) and for one customer. By using MLM it is possible to get larger devices (even up to wafer size) or larger number of dies and wafers up to few batches typically. MLM is a smooth continuation from MPW production volumes upwards and therefore this may support also small/mid size volume production. Not all foundries support MLM arrangements.

Due to the complexity of the technologies available and the need to run MPC/MPWs smoothly, following the rules, timing of the designs and use of suggested design tools are critical for leveraging the benefits of MPC/MPW services. However every service provider has its own practicalities including design data, die sizes, design rules, device models, design tools used, ready IP blocks available and timing etc.

Turn around times and cost of MPC and MPW services depend on the manufacturing technology and designs/prototypes are typically available as bare dies or as packaged devices. Deliveries are typically untested, but in most of the cases the quality of the manufacturing process is guaranteed by the measurement results of process control monitor(s) (PCM) or similar.

MPC approach was one of the first hardware service platforms in semiconductor industry, and the more flexible MPW arrangement is continuing to be part of well established microelectronics manufacturing and foundry model not limited to silicon IC manufacturing but spreading into other semiconductor production areas for cost effective prototyping, development and research.

Companies and services[edit]

Many MPC/MPW arrangements were first nationwide activities, but were expanded international, global co-operative activities based on emerging foundry technologies:

CMC Microsystems[edit]

CMC Microsystems is a not-for-profit organization in Canada accelerating research and innovation in advanced technologies. Founded in 1984, CMC lowers barriers to designing, manufacturing, and testing prototypes in microelectronics, photonics, quantum, MEMS, and packaging. CMC technology platforms such as the ESP (Electronic Sensor Platform) jumpstart R&D projects, enabling engineers and scientists to achieve results sooner and at a lower cost. Annually, more than 700 research teams from companies and 100 academic institutions around the world access CMC's services and turn more than 400 designs into prototypes through its global network of manufacturers. This support enables 400 industrial collaborations and 1,000 trained HQP to join industry each year, and these relationships assist in the translation of academic research into outcomes—publications, patents, and commercialization.

Muse Semiconductor[edit]

Muse Semiconductor was founded in 2018[8] by former eSilicon employees.[9][10] The company name "Muse" is an informal acronym for MPW University SErvice.[8] Muse focuses on serving the MPW needs of microelectronics researchers.[11][12] Muse supports all TSMC technologies and offers an MPW service with a minimum area of 1mm^2 for some technologies.[13][14] Muse is a member of the TSMC University FinFET Program. [15][16]


The first well known MPC service was MOSIS (Metal Oxide Silicon Implementation Service), established by DARPA as a technical and human infrastructure for VLSI. MOSIS began in 1981 after Lynn Conway organized the first VLSI System Design Course at MIT in 1978 and the course produced 'multi-university, multi-project chip-design demonstration'[17] delivering devices to the course participants in 1979.[18][19] The designs for the MPC were gathered using ARPANET. The technical background additionally to education was to develop and research in a cost effective way new computer architectures without limitations of standard components.[20] MOSIS primarily services commercial users with MPW arrangement. MOSIS has ended their University Support Program.[21] With MOSIS, designs are submitted for fabrication using either open (i.e., non-proprietary) VLSI layout design rules or vendor proprietary rules. Designs are pooled into common lots and run through the fabrication process at foundries. The completed chips (packaged or bare dies) are returned to customers.


The first international silicon IC MPC service NORCHIP was established among four nordic countries (Denmark, Finland, Norway and Sweden) 1981 delivering first chips 1982.[22] It was funded by Nordic Industrial Fund and R&D financing organisations from each participating country. Targets were training and to enhance cooperation between research and industry specifically in areas of analog and digital signal processing and power management Integration.[23] Parallel with NORCHIP organised by same nordic countries there was Nordic GaAs program NOGAP 1986-1989, which produced modelling techniques for GaAs IC devices, and demonstrators of high speed digital and RF/analog MMICs. From 1989 to 1995 nordic universities, research institutes and small companies have been participating in european EUROCHIP and from 1995 on wards in EUROPRACTICE. [24][25]


CMP a French company working since 1981 started MPC operation with NMOS offering but expanding offering to CMOS and various other technologies.[26][27] CMP was also the first official pan-continental MPC/MPW operation having link to MOSIS among other MPW arrangements globally. CMPs services have included variety of technologies including multi-chip modules (MCMs) suitable for the packaging of chiplets.[28]


Similar arrangements utilising silicon IC technology were also AusMPC in Australia starting 1981, E.I.S. project (started year 1983)[29] in Germany and EUROEAST (1994-1997) covering Romania, Poland, Slovak Republic, Hungary, Czech Republic, Bulgaria, Estonia, Ukraine, Russia, Latvia, Lithuania and Slovenia. BERCHIP MPC activity starting in 1994 was organised in Latin America. Numerous MPW services have been launched since 1994 worldwide.


Efabless enables a platform for ICs/SoCs designed by solely using open source design tools and community models. It started operations year 2020 as a start up with limited access to manufacturing technologies from SkyWater Technology and offering few annual runs as synched with US university academic year.[30] Within stabilised finansing and operations Efabless platform is targeted globally additionally to universities also for research institutes, small possibly start up phase companies and specifically as a first step to convert and test transition from FPGA to an integrated circuit.


  1. ^ Wu, M.-C.; Lin, R.-B. (2005). "Multiple Project Wafers for Medium-Volume IC Production". 2005 IEEE International Symposium on Circuits and Systems. pp. 4725–4728. doi:10.1109/ISCAS.2005.1465688. ISBN 0-7803-8834-8. S2CID 16510670.
  2. ^ Noonan, J. A. (1986). "Investigation into methods and analysis of computer aided design of VLSI circuits". Master Thesis, the Department of Electrical and Electronic Engineering, the University of Adelaide.
  4. ^ "MPW". SMART Photonics.
  5. ^ "An integrated modular service for microfluidics, μBUILDER program".
  6. ^ Grinde, C.; Welham, C. (2008). "μBUILDER: The easy and low cost road to advanced microsystems". 2008 15th IEEE International Conference on Electronics, Circuits and Systems. pp. 17–18. doi:10.1109/ICECS.2008.4675128. ISBN 978-1-4244-2181-7.
  7. ^ Pann, P. (2009). "Prototyping and testing of analog integrated circuits". Proceedings - 1st Asia Symposium on Quality Electronic Design: 173–177. doi:10.1109/ASQED.2009.5206277. S2CID 2987670.
  8. ^ a b "FAQ | Muse Semiconductor". musesemi. Retrieved 2022-09-04.
  9. ^ "FAQ | Muse Semiconductor". musesemi.
  10. ^ McLellan, Paul. "Quoting Automatically the eSilicon Way". Semiwiki. Retrieved 2022-09-04.
  11. ^ "Home | Muse Semiconductor". musesemi. Retrieved 2022-09-04.
  12. ^ "Dear Colleague Letter: Supplements for Access to Semiconductor Fabrication (ASF) (nsf22113) | NSF - National Science Foundation". Retrieved 2022-09-06.
  13. ^ Example of MPW pricing
  14. ^ A New Era of Silicon Prototyping in Computer Architecture Research
  15. ^ "TSMC University FinFET Program - Taiwan Semiconductor Manufacturing Company Limited". Retrieved 30 March 2023.
  16. ^ "TSMC University FinFET Program Services and Price | Muse Semiconductor".
  17. ^ Conway, Lynn; Suchman, Lucy (February 28, 2021). "Conway-Suchman conversation". Conway Suchman Conversation – via
  18. ^ "Lynn Conway's 1978 MIT VLSI System Design Course".
  19. ^ Conway, L. (1982). "The MPC adventures: Experiences with the generation of VLSI design and implementation methodologies" (PDF). Microprocessing and Microprogramming Number 4. 10 (4): 209–228. doi:10.1016/0165-6074(82)90054-0.
  20. ^ "VLSI Implementation Services: From MPC79 to MOSIS and Beyond".
  21. ^ "MOSIS".
  22. ^ Tenhunen, H.; Nielsen, I.-R. (1994). "Microelectronics R&D cooperation in the nordic countries". Analog Integrated Circuits and Signal Processing. 5 (3): 195–197. doi:10.1007/BF01261411. S2CID 62771908.
  23. ^ Olesen, O.; Svensson, C. (1984). "NORCHIP, a silicon brokers model". Integration. 2: 3–13. doi:10.1016/0167-9260(84)90003-8.
  24. ^ Kemppinen, E.; Järvinen, E.; Närhi, T. (1988). "Design of an L-band monolithic GaAs receiver front-end with low power consumption". 1988., IEEE International Symposium on Circuits and Systems. Vol. 3. pp. 2535–2538. doi:10.1109/ISCAS.1988.15458. S2CID 57998893.
  25. ^ Andersson, M.; Åberg, M.; Pohjonen, H. (1988). "Simultaneous extraction of GaAs MESFET channel and gate diode parameters and its application to circuit simulation". 1988., IEEE International Symposium on Circuits and Systems. Vol. 3. pp. 2601–2604. doi:10.1109/ISCAS.1988.15474. S2CID 62628680.
  26. ^ Courtois, B.; Delori, H.; Karam, J.M.; Paillotin, F.; Torki, K. (1996). "CMP services: Basic principles and developments". 2nd International Conference on ASIC. pp. 417–420. doi:10.1109/ICASIC.1996.562841. S2CID 108800823.
  27. ^ Torki, K.; Courtois, B. (2001). "CMP: The access to advanced low cost manufacturing". Proceedings 2001 International Conference on Microelectronic Systems Education. pp. 6–9. doi:10.1109/MSE.2001.932392. ISBN 0-7695-1156-2. S2CID 30387757.
  28. ^ Li, Tao; Hou, Jie; Yan, Jinli; Liu, Rulin; Yang, Hui; Sun, Zhigang (2020). "Chiplet Heterogeneous Integration Technology—Status and Challenges". Electronics. 9 (4): 670. doi:10.3390/electronics9040670. S2CID 218776269.
  29. ^ "The E.I.S. Project and other EDA Achievements".
  30. ^ "Google Partners with SkyWater and Efabless to Enable Open Source Manufacturing of Custom ASICs". Skywater Technology. 2020-11-12. Retrieved 2022-06-15.

External links[edit]