Multi-project wafer service

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Multi-project chip (MPC), and multi-project wafer (MPW) semiconductor manufacturing arrangements allow to share mask and microelectronics wafer fabrication cost between several designs or projects.

MPC consisting of five CMOS IC designs and few test N- and PMOS transistors for manufacturing acceptance

With MPC arrangement one chip is a combination of several designs and this combined chip is then repeated all over the wafer during the manufacturing. MPC arrangement produces typically roughly equal number of chip designs per wafer.

A wafer consisting of MPC designs all over the wafer and five process control monitor (PCM) designs for ensuring good quality of the processing

With MPW arrangement it is possible by using novel mask making and expose systems in photolitography during IC manufacturing to handle different sizes of chips and therefore to produce different number of designs/projects per wafer. MPW has progressed based on experience gained from the older MPC procedures additionally enabling more effective support for different phases and needs of manufacturing volumes of different designs/projects. MPW arrangement can support flexibly education, research of new circuit architectures and structures, prototyping and even small volume production.[1][2]

A multi-project wafer consisting of several different unequal number of designs/projects.

Worldwide, several MPW services are available from companies, semiconductor foundries and from government-supported institutions. Originally both MPC and MPW arrangements were introduced for integrated circuit (IC) education and research and some MPC/MPW services/gateways are aimed for non-commercial use only. Selecting right service platform already at prototyping phase ensures gradual scaling up production via MPW services taking into account the few practical rules of the selected service.

MPC/MPW arrangements have also been applied for microelectromechanical systems (MEMS),[3] integrated photonics[4] like silicon photonics fabrication and microfluidics.[5][6]

A refinement of MPW is multi-layer mask (MLM) arrangement, where limited number of masks (like 4) is changed during manufacturing at exposure phase. Rest of the masks are the same from the chip to chip on the whole wafer.[7] MLM approach is well suited for several specific cases:

  • Large (even possibly whole wafer) designs like detectors, where by using few mask layers it is possible to form functional devices
  • Making different versions of one design/project like for different performance or standards of one design

Typically MLM approach is used for one wafer batch (consisting of several wafers depending on the fabrication line) and for one customer. By using MLM it is possible to get larger devices (even up to wafer size) or larger number of dies and wafers up to few batches typically. MLM is a smooth continuation from MPW production volumes upwards and therefore this may support also small/mid size volume production. All foundries do not support MLM approach.

Due to complexity of the technologies available and running MPC/MPWs smoothly several rules and timing of the designs are critical for maximizing the benefits of MPC/MPW services. However every service provider has own practicalities including design data, die sizes, design rules, device models, ready IP blocks available and timing etc.

Turn around times and cost of MPC and MPW services depend on the manufacturing technology and designs/prototypes are typically available as bare dies or as packaged devices. Deliveries are untested, but in most of the cases the quality of the manufacturing process is guaranteed by the measurement results of process control monitor(s) (PCM) or similar.

MPC approach was one of the first hardware service platforms in semiconductor industry and more flexible MPW arrangement is continuing to be part of well established IC manufacturing and foundry model not limited to silicon IC manufacturing but spreading into other semiconductor production areas for cost effective prototyping, development and research.

Short history of MPC and MPW[edit]

The first well known MPC service was MOSIS (Metal Oxide Silicon Implementation Service), established by DARPA as a technical and human infrastructure for VLSI. MOSIS began in 1981 after Lynn Conway organized the first VLSI System Design Course at MIT in 1978 and the course produced ‘multi-university, multi-project chip-design demonstration’[8] delivering devices to the course participants in 1979.[9][10] The designs for the MPC were gathered using ARPANET. The technical background additionally to education was to develop and research in a cost effective way new computer architectures without limitations of standard components.[11] MOSIS primarily services commercial users with MPW arrangement now but also continues to serve university students and researchers. With MOSIS, designs are submitted for fabrication using either open (i.e., non-proprietary) VLSI layout design rules or vendor proprietary rules. Designs are pooled into common lots and run through the fabrication process at foundries. The completed chips (packaged or bare dies) are returned to customers.

The first international silicon IC MPC service NORCHIP was established among four nordic countries (Denmark, Finland, Norway and Sweden) 1981 delivering first chips 1982.[12] It was funded by Nordic Industrial Fund and R&D financing organisations from each participating country. Targets were training and to enhance cooperation between research and industry specifically in areas of analog and digital signal processing and power management Integration.[13] Parallel with NORCHIP organised by same nordic countries there was Nordic GaAs program NOGAP 1986-1989, which produced modelling techniques for GaAs IC devices, and demonstrators of high speed digital and RF/analog MMICs.[14][15]

CMP in France starting year 1981,[16][17] NORCHIP and NOGAP were the key enablers for the Pan-European MPC/MPW arrangement called EUROCHIP (1989-1995) and its follower EUROPRACTISE from 1995 on wards. CMP was also the first official pan-continental MPC/MPW operation having link to MOSIS among other MPW arrangements globally. CMPs services have included variety of technologies for digital, mixed signal, analog, high speed and power handling as well as multi-chip modules (MCMs) suitable for the packaging of chiplets.[18]

Similar arrangements utilising silicon IC technology were also AusMPC in Australia starting 1981, E.I.S. project (started year 1983)[19] in Germany and EUROEAST (1994-1997) covering Romania, Poland, Slovak Republic, Hungary, Czech Republic, Bulgaria, Estonia, Ukraine, Russia, Latvia, Lithuania and Slovenia. BERCHIP MPC activity starting in 1994 was organised in Latin America. Numerous MPW services have been launched since 1994 worldwide.

Muse Semiconductor was founded in 2018[20] by former eSilicon employees [1]. The company name "Muse" is an informal acronym for MPW University SErvice.[21] Muse focuses on serving the MPW and low volume IC fabrication needs of microelectronics researchers and companies referred by researchers around the world [2]. Muse supports all TSMC technologies and offers a Shared Block service with a minimum area of 1 mm^2 for some technologies.[22][23]

Because obvious cost saving and speed up of prototyping benefits several large companies have organised internal MPC/MPWs and many silicon foundries started to offer MPW services as part of their service platforms for various integration technologies worldwide.

References[edit]

  1. ^ Wu, M.-C.; Lin, R.-B. (2005). "Multiple Project Wafers for Medium-Volume IC Production". Proceedings - IEEE International Symposium on Circuits and Systems: 4725–4728. doi:10.1109/ISCAS.2005.1465688.
  2. ^ Noonan, J. A. (1986). Investigation into methods and analysis of computer aided design of VLSI circuits. Master thesis, The Department of Electrical and Electronic Engineering, The University of Adelaide.
  3. ^ "EUROPRACTICE MEMS MPW".
  4. ^ "Example of photonics MPW".
  5. ^ "An integrated modular service for microfluidics, µBUILDER program".
  6. ^ Grinde, C.; Welham, C. (2008). "μBUILDER: The easy and low cost road to advanced microsystems". Proceedings -15th IEEE International Conference on Electronics, Circuits and Systems: 17–18. doi:10.1109/ICECS.2008.4675128.
  7. ^ Pann, P. (2009). "Prototyping and testing of analog integrated circuits". Proceedings - 1st Asia Symposium on Quality Electronic Design: 173–177. doi:10.1109/ASQED.2009.5206277.
  8. ^ "Conway-Suchman conversation".
  9. ^ "The M.I.T. 1978 VLSI System Design Course".
  10. ^ Conway, L. (1982). "The MPC adventures: Experiences with the generation of VLSI design and implementation methodologies". Microprocessing and Microprogramming number 4. 10: 209–228. doi:10.1016/0165-6074(82)90054-0.
  11. ^ "MOSIS 1st deliveries".
  12. ^ Tenhunen, H.; Nielsen, I.-R. (1994). "Microelectronics R&D cooperation in the nordic countries". Analog Integrated Circuits and Signal Processing: 195–197. doi:10.1007/BF01261411.
  13. ^ Olesen, O.; Svensson, C. (1984). "NORCHIP, a silicon brokers model". INTEGRATION, The VLSI Journal. 2: 3–13.
  14. ^ Kemppinen, E.; Järvinen, E.; Närhi, T. (1988). "Design of an L-band monolithic GaAs receiver front-end with low power consumption". IEEE International Symposium on Circuits and Systems. 3: 2535–2538. doi:10.1109/ISCAS.1988.15458.
  15. ^ Andersson, M.; Åberg, M.; Pohjonen, H. (1988). "Simultaneous extraction of GaAs MESFET channel and gate diode parameters and its application to circuit simulation". IEEE International Symposium on Circuits and Systems. 3: 2601–2604. doi:10.1109/ISCAS.1988.15474.
  16. ^ Courtois, B.; Delori, H.; Karam, J.M.; Paillotin, F.; Torki, K. (1996). "CMP services: basic principles and developments". Proceedings of 2nd International Conference on ASIC, Shanghai, China: 417–420. doi:10.1109/ICASIC.1996.562841.
  17. ^ Torki, K.; Courtois, B. (2001). "CMP: the access to advanced low cost manufacturing services". Proceedings 2001 International Conference on Microelectronic Systems Education: 6–9. doi:10.1109/MSE.2001.932392.
  18. ^ Li, T.; et, al. (2020). "Chiplet Heterogeneous Integration Technology—Status and Challenges". Electronics. 9 (670): 1–12. doi:10.3390/electronics904067.
  19. ^ "E.I.S. short history".
  20. ^ https://www.musesemi.com/faq
  21. ^ https://www.musesemi.com/faq
  22. ^ https://www.musesemi.com/shared-block-tapeout-pricing Example of MPW pricing
  23. ^ https://www.csl.cornell.edu/~cbatten/pdfs/torng-brgtc2-slides-riscvday2018.pdf A New Era of Silicon Prototyping in Computer Architecture Research

Examples of some MPC/MPW services in alphabetical order[edit]