A multigate device or multiple gate field-effect transistor (MuGFET) refers to a MOSFET (metal–oxide–semiconductor field-effect transistor) which incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor (MIGFET). Multigate transistors are one of the several strategies being developed by CMOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's Law.
Development efforts into multigate transistors have been reported by AMD, Hitachi, IBM, Infineon Technologies, Intel Corporation, TSMC, Freescale Semiconductor, University of California, Berkeley and others and the ITRS predicted correctly that such devices will be the cornerstone of sub-32 nm technologies. The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-k/metal gate materials.
Dozens of multigate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and number of channels/gates (2, 3, or 4).
Planar double-gate transistor
Planar double-gate transistors employ conventional planar (layer by layer) manufacturing processes to create double-gate devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors the drain-source channel is sandwiched between two independently fabricated gate/gate oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates.
FlexFET is a planar, independently double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. FlexFET is a true double-gate transistor in that (1) both the top and bottom gates provide transistor operation, and (2) the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa. Flexfet was developed, and is manufactured, by American Semiconductor, Inc.
The term FinFET (Fin Field Effect Transistor) was coined by University of California, Berkeley researchers (Profs. Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) to describe a nonplanar, double-gate transistor built on an SOI substrate, based on the earlier DELTA (single-gate) transistor design.  The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a thin silicon "fin", which forms the body of the device. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. The Wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects.
In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD, IBM, and Freescale describe their double-gate development efforts as FinFET development whereas Intel avoids using the term to describe their closely related tri-gate architecture (see #Tri-gate transistor). In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates.
A 25-nm transistor operating on just 0.7 volt was demonstrated in December 2002 by TSMC (Taiwan Semiconductor Manufacturing Company). The "Omega FinFET" design is named after the similarity between the Greek letter omega (Ω) and the shape in which the gate wraps around the source/drain structure. It has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.
FinFET can also have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.
In 2012, Intel started using FinFETs for its future commercial devices. Leaks suggest that Intel's FinFET shape has an unusual shape of a triangle rather than rectangle and it is speculated that this might be either because a triangle has a higher structural strength and can be more reliably manufactured or because a triangular prism has a higher area to volume ratio than a rectangular prism thus increasing switching performance.
In September 2012, GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014. The next month, the rival company TSMC announced start early or "risk" production of 16 nm FinFETS in November 2013.
AMD announced a 14 nm FinFET GPU based on their Polaris chip architecture in January, 2016. The company expects the design to provide a "generational jump in power efficiency" while also offering stable frame rates for graphics, gaming, virtual reality, and multimedia applications.
As of today, mobile devices have adopted the use of FinFET on its manufacturing process. Qualcomm's lineup of chipsets in 2016 are manufactured using FinFET technology. smartphones from the ASUS ZenFone 3 family and all Huawei/Honor Kirin 950- and 650-based devices have adopted FinFET. FinFET is by far the most significant improvement towards battery life of mobile devices thus far. 
Tri-gate or 3D transistor (not to be confused with 3D microchips) fabrication is used by Intel Corporation for the nonplanar transistor architecture used in Ivy Bridge, Haswell and Skylake processors. These transistors employ a single gate stacked on top of two vertical gates allowing for essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than current transistors. This allows up to 37% higher speed, or a power consumption at under 50% of the previous type of transistors used by Intel.
Intel explains, "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)." Intel has stated that all products after Sandy Bridge will be based upon this design.
Intel was the first company to announce this technology. In September 2002, Intel announced their creation of 'Triple-Gate Transistors' to maximize 'transistor switching performance and decreases power-wasting leakage'. A year later in September 2003, AMD announced it was working on similar technology at the International Conference on Solid State Devices and Materials. No further announcements of this technology were made until Intel's announcement in May 2011 although it was stated at IDF 2011, that they demonstrated a working SRAM chip based on this technology at IDF 2009.
On April 23, 2012 Intel released a new line of CPUs, termed Ivy Bridge, which feature tri-gate transistors. Intel has been working on its tri-gate architecture since 2002, but it took until 2011 to work out mass production issues. The new style of transistor was described on May 4, 2011, in San Francisco. Intel factories are expected to make upgrades over 2011 and 2012 to be able to manufacture the Ivy Bridge CPUs. As well as being used in Intel's Ivy Bridge chips for desktop PCs, the new transistors will also be used in Intel's Atom chips for low powered devices.
The term tri-gate is sometimes used generically to denote any multigate FET with three effective gates or channels.
Gate-all-around (GAA) FET
Gate-all-around FETs are similar in concept to FinFETs except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully characterized both theoretically and experimentally. They have also been successfully etched onto InGaAs nanowires, which have a higher electron mobility than silicon.
Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. As the size decreases, planar transistors increasingly suffer from the undesirable short-channel effect, especially "off-state" leakage current, which increases the idle power required by the device.
In a multigate device, the channel is surrounded by several gates on multiple surfaces. It thus provides a better electrical control over the channel, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. Multigate transistors also provide a better analog performance due to a higher intrinsic gain and lower channel length modulation. These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics.
The primary challenges to integrating nonplanar multigate devices into conventional semiconductor manufacturing processes include:
- Fabrication of a thin silicon "fin" tens of nanometers wide
- Fabrication of matched gates on multiple sides of the fin
BSIMCMG106.0.0, officially released on March 1, 2012 by UC Berkeley BSIM Group, is the first standard model for FinFETs. BSIM-CMG is implemented in Verilog-A. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees closely with the 2-D device simulation results. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD= 1).
All of the important Multi-Gate (MG) transistor behavior is captured by this model. Volume inversion is included in the solution of Poisson’s equation, hence the subsequent I-V formulation automatically captures the volume inversion effect. Analysis of electro-static potential in the body of MG MOSFETs provided a model equation for short-channel effects (SCE). The extra electrostatic control from the end-gates (top/bottom gates) (triple or quadruple-gate) is also captured in the short channel model.
- Risch, L. "Pushing CMOS Beyond the Roadmap", Proceedings of ESSCIRC, 2005, p. 63
- Table39b Archived September 27, 2007, at the Wayback Machine.
- "3N201 (Motorola) - Dual Gate Mosfet Vhf Amplifier". Doc.chipfind.ru. Retrieved 2014-03-10.
- "3SK45 datasheet pdf datenblatt - Hitachi Semiconductor - SILICON N-CHANNEL DUAL GATE MOSFET". Alldatasheet.com. Retrieved 2014-03-10.
- "BF1217WR" (PDF). Retrieved 2015-05-10.
- Wong, H-S.; Chan, K.; Taur, Y. (December 10, 1997). "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel". Electron Devices Meeting, 1997. IEDM '97. Technical Digest: 427–430. doi:10.1109/IEDM.1997.650416. ISBN 0-7803-4100-7. ISSN 0163-1918.
- Wilson, D.; Hayhurst, R.; Oblea, A.; Parke, S.; Hackler, D. "Flexfet: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope" SOI Conference, 2007 IEEE International Archived April 3, 2015, at the Wayback Machine.
- Xuejue Huang; Wen-Chin Lee; Kuo, C.; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. doi:10.1109/16.918235.
- Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). "Impact of the vertical SOI 'DELTA' structure on planar device technology" (PDF). IEEE Transactions on Electron Devices. 38 (6): 1419–1424. doi:10.1109/16.81634. Archived from the original (PDF) on 2016-12-01.
- Hisamoto, D. et al. (1991) "Impact of the vertical SOI 'Delta' Structure on Planar Device Technology" IEEE Trans. Electron. Dev. 41 p. 745.
- Chenming Hu; Bokor, J.; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. doi:10.1109/16.887014.
- "AMD Newsroom". Amd.com. 2002-09-10. Archived from the original on 2010-05-13. Retrieved 2015-07-07.
- "Intel Silicon Technology Innovations". Intel.com. Archived from the original on September 3, 2011. Retrieved 2014-03-10.
- "IEEE Xplore Abstract - Dual- Independent-Gate FinFETs for Low Power Logic Circuits". Ieeexplore.ieee.org. doi:10.1109/TCAD.2010.2097310. Archived from the original on December 14, 2013. Retrieved 2014-03-10.
- "Intel's FinFETs are less fin and more triangle". EE Times. Retrieved 2014-03-10.
- "Globalfoundries looks leapfrog fab rivals with new process". EE Times. Retrieved 2014-03-10.
- "TSMC taps ARM's V8 on road to 16 nm FinFET". EE Times. Retrieved 2014-03-10.
- Josephine Lien, Taipei; Steve Shen, [Monday 31 March 2014]. "TSMC likely to launch 16 nm FinFET+ process at year-end 2014, and "FinFET Turbo" later in 2015-16". DIGITIMES. Retrieved 2014-03-31.
- "AMD Demonstrates Revolutionary 14nm FinFET Polaris GPU Architecture". AMD. Retrieved 2016-01-04.
- Kee, Kok (19 October 2016). "Review – ZenFone 3: Beautiful And Powerful". Nasi Lemak Tech. Nasi Lemak Tech. Retrieved 1 December 2016.
- Kee, Kok (29 June 2016). "Explaining the chipset; feat. HiSilicon". Nasi Lemak Tech. Nasi Lemak Tech. Retrieved 1 December 2016.
- Kee, Kok (20 October 2016). "Huawei's Kirin 960 Summarized: What You Need To Know". Nasi Lemak Tech. Nasi Lemak Tech. Retrieved 1 December 2016.
- Kee, Kok (5 October 2016). "Why And How Your 3,000mAh Battery Can Last Longer". Nasi Lemak Tech. Nasi Lemak Tech. Retrieved 1 December 2016.
- Cartwright J (2011). "Intel enters the third dimension". Nature. doi:10.1038/news.2011.274. Retrieved 2015-05-10.
- Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium (ElectroIQ 2012) Archived April 15, 2012, at the Wayback Machine.
- "Below 22nm, spacers get unconventional: Interview with ASM". ELECTROIQ. Retrieved 2011-05-04.
- [dead link]
- "AMD Details Its Triple-Gate Transistors". Xbitlabs.com. Retrieved 2014-03-10.
- "IDF 2011: Intel Looks to Take a Bite Out of ARM, AMD With 3D FinFET Tech". DailyTech. Retrieved 2014-03-10.
- Miller, Michael J. PC Magazine http://forwardthinking.pcmag.com/pc-hardware/296972-intel-releases-ivy-bridge-first-processor-with-tri-gate-transistor. Missing or empty
- "Intel Reinvents Transistors Using New 3-D Structure". Intel. Retrieved 5 April 2011.
- "Transistors go 3D as Intel re-invents the microchip". Ars Technica. 5 May 2011. Retrieved 7 May 2011.
- Murray, Matthew (4 May 2011). "Intel's New Tri-Gate Ivy Bridge Transistors: 9 Things You Need to Know". PC Magazine. Retrieved 7 May 2011.
- Singh N, et al. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters. 27 (5): 383–386. Bibcode:2006IEDL...27..383S. doi:10.1109/LED.2006.873381.
- Dastjerdy, E.; Ghayour, R.; Sarvari, H. (August 2012). "Simulation and analysis of the frequency performance of a new silicon nanowire MOSFET structure". Physica E. 45: 66–71. Bibcode:2012PhyE...45...66D. doi:10.1016/j.physe.2012.07.007.
- "First Experimental Demonstration of Gate-all-around III-V MOSFETs by Top-down Approach" (PDF). Retrieved 2015-05-10.
- Subramanian V (2010). "Multiple gate field-effect transistors for future CMOS technologies". IETE Technical Review. 27: 446–454. Archived from the original on March 23, 2012.
- Subramanian (5 Dec 2005). "Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs". Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International: 898–901.
- "BSIMCMG Model". UC Berkeley.