Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.
- 1 Pitch Splitting
- 2 Sidewall Image Transfer
- 3 Self-aligned contact/via patterning
- 4 Spacer-is-Dielectric (SID) SADP
- 5 Directed Self-Assembly (DSA)
- 6 Other multi-patterning techniques
- 6.1 Layout Splitting
- 6.2 Wire Widening with SADP
- 6.3 Wire Widening with SAQP
- 6.4 Self-Aligned Triple Patterning (SATP)
- 6.5 Grid Routing for Mostly Minimum Pitch SADP and SAQP
- 6.6 Cut Redistribution
- 6.7 Track Re-ordering
- 6.8 Self-trimming outer loops on spacers
- 6.9 Cut Selection Layer
- 6.10 Tilted Ion Implantation
- 6.11 Protrusion Spacer Cutting and Linking Features
- 6.12 Complementary polarity exposures
- 6.13 Self-Aligned Blocking
- 7 EUV Multiple Patterning Possibilities
- 8 Specific Implementations for 2D Contact/Via/Cut Patterns
- 9 Multipatterning Implementations
- 10 Industrial Adoption
- 11 References
The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.
A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.
This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density.
A variation on this approach which eliminates the first hardmask etch is resist freezing, which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method, where the freezing is accomplished by surface hardening of the first resist layer.
In recent years, the scope of the term 'pitch splitting' has gradually been expanded to include techniques involving sidewall spacers.
Sidewall Image Transfer
In spacer patterning, a spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Double Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.
As pitch splitting has become more difficult due to possible differences in feature positions between different exposed parts, sidewall image transfer (SIT) has become more recognized as the necessary approach. The SIT approach typically requires a spacer layer to be formed on an etched feature's sidewall. If this spacer corresponds to a conducting feature, then ultimately it must be cut at no less than two locations to separate the feature into two or more conducting lines as typically expected. On the other hand, if the spacer corresponds to a dielectric feature, cutting would not be necessary. The prediction of how many cuts would be needed for advanced logic patterns has been a large technical challenge. Many approaches for spacer patterning have been published (some listed below), all targeting the improved management (and reduction) of the cuts.
As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.
The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other. Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking.
The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.
When SADP is repeated, an additional halving of the pitch is achieved. This is often referred to as Self-Aligned Quadruple Patterning (SAQP). With 76 nm being the expected minimum pitch for a single immersion lithography exposure, 19 nm pitch is now accessible with SAQP.
Self-aligned contact/via patterning
Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.
Spacer-is-Dielectric (SID) SADP
In self-aligned double patterning (SADP), the number of cut/block masks may be reduced or even eliminated in dense patches when the spacer is used to directly pattern inter-metal dielectric instead of metal features. The reason is the cut/block locations in the core/mandrel features are already patterned in the first mask. There are secondary features which emerge from the gaps between spacers after further patterning. The edge between a secondary feature and the spacer is self-aligned with the neighboring core feature.
Directed Self-Assembly (DSA)
The number of masks used for sidewall spacer patterning may be reduced with the use of directed self-assembly (DSA) due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure. Alternatively, the cut pattern itself may be generated as a DSA step. Likewise, a split via layout may be recombined in pairs.
Much progress had been reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy). The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders. However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.
The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter. A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)−1/2, where a is the statistical polymer chain length. Moreover, χN > 10.5 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π2)1/3aN2/3χ1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.
DSA has not yet been implemented in manufacturing, due to defect concerns, where a feature does not appear as expected by the guided self-assembly.
Other multi-patterning techniques
There have been numerous concerns that multiple patterning diminishes or even reverses the node-to-node cost reduction expected with Moore's Law. EUV is more expensive than three 193i exposures (i.e., LELELE), considering the throughput. Moreover, EUV is more liable to print smaller mask defects not resolvable by 193i. Some aspects of other considered multi-patterning techniques are discussed below.
Commonly, some layers consist of patterns which require different exposure conditions, e.g., different dipole illuminations for horizontal vs. vertical features. This would result in breaking the layout into two or more different masks, each with a customized illumination. More generally, this technique, applied to each mask, is called Source-Mask-Optimization (SMO). Although EUV has been targeted for single exposure patterning, the need for SMO at relatively loose design rules to address shadowing still necessitates the use of double or multiple patterning at 10 nm and beyond.
Wire Widening with SADP
Largely motivated by timing optmization, in SADP layouts, some wires may be widened to 3x the minimum metal width. This is actually advantageous within the SID SADP scheme, as the core pitch can now be expanded to at least 3x the minimum pitch.
Wire Widening with SAQP
Similarly to SADP, wire widening can also take place in context of SAQP, with the use of opposite polarity masks for cutting and blocking.
Self-Aligned Triple Patterning (SATP)
Self-aligned triple patterning has been considered as a promising successor to SADP, due to its introduction of a second spacer offering additional 2D patterning flexibility and higher density. A total of two masks (mandrel and trim) is sufficient for this approach. The only added cost relative to SADP is that of depositing and etching the second spacer. The main disadvantage of SATP succeeding SADP is that it would only be usable for one node. For this reason, self-aligned quadruple patterning (SAQP) is more often considered. On the other hand, the conventional SID SADP flow may be extended quite naturally to triple patterning, with the second mask dividing the gap into two features.
Grid Routing for Mostly Minimum Pitch SADP and SAQP
Toshiba had proposed the grid routing approach for layouts with mostly consistent pitch, this pitch requiring the spacer-based multi-patterning. The approach allows for 2D layout patterns to be realized even with SADP and SAQP. In particular, for SADP, the cut or trim mask can in principle be eliminated, due to the fact that the spacer does not result in conductive loops. For SAQP, the 2nd spacer, strictly speaking, also defines non-conductive loops, but the remaining unoccupied space between the 2nd spacers represents a conductive feature, which requires trimming. Fortunately, the separation between such trim locations is extended over several feature widths, which simplifies the cutting arrangement. The main concern for mostly minimum pitch in the layout is maximized capacitance, i.e., the minimum pitch results in the maximum capacitance per unit length.
The number of cut masks can also be reduced by allowed redistribution of cuts. Such redistribution can lead to merged or aligned cut regions, which also goes well with the implementation of directed self-assembly, described above.
For metal layers, the metal is often divided into segments lying along tracks. By ordering the tracks in an optimum fashion, multiple exposures may be avoided for cutting the metal lines in the specified locations.
Self-trimming outer loops on spacers
U. S . Patent 6632741, assigned to IBM, teaches a method to remove unwanted portions of material at the outer edge of a spacer pattern. After the spacer pattern is formed, and before the mandrel (or core) features are removed, a gapfill material is deposited to completely fill the narrow gaps between spacers as well as conformally coat the outer wider gaps. An isotropic etch is able to remove the gapfill material in the outer wider gap locations completely but only partly remove the gapfill material in the narrow gaps. The outer spacer can then be removed in the same way, avoiding looping patterns. The end result is that only the spacer-patterned dense array features remain.
Cut Selection Layer
The cut pattern may also be generated by spacer patterning with pattern trimming/cutting, rather than by direct exposure. The key benefit is that the cut pattern will not suffer from CD errors associated with the exposure process, such as dose error, focus error, etc. Cut distances are also much larger so that one cut selection mask combined with the cut grid mask has been shown to be sufficient. In some cases, the cut or block selection may not even need a mask.
Tilted Ion Implantation
Tilted ion implantation was proposed in 2016 by the University of Berkeley as an alternative method of achieving the same result as spacer patterning. Instead of core or mandrel patterns supporting deposited spacers, an ion masking layer pattern shields an underlying layer from being damaged by ion implantation, which leads to being etched away in a subsequent process. The process requires the use of angled ion beams which penetrate to just the right depth, so as not to damage already processed layers underneath. Also, the ion masking layer must behave ideally, i.e., blocking all ions from passing through, while also not reflecting off the sidewall. The latter phenomenon would be detrimental and defeat the purpose of the ion masking approach. Trenches as small as 9 nm have been achieved with this approach, using 15 keV Ar+ ion implantation at 15-degree angles into a 10 nm thermal SiO2 masking layer. A fundamental aspect of this approach is the correlation between damage width and damage pitch; both widen at the same time for fixed ion mask height and ion beam angle.
Protrusion Spacer Cutting and Linking Features
Mandrel or spacer core patterns can be designed to cut their own spacer patterns. A pair of opposing line protrusions can effectively squeeze out any feature in between if a spacer with a thickness exceeding half the distance between the protrusions is deposited, followed by the feature deposition. This is ideal for use in SID SADP schemes. A similar approach is the use of linked features, i.e., narrow constrictions which separate features in spacer patterning without cutting.
The protrusion cutting technique helps reduce the amount of cutting that is needed, and also enables the grid routing method described by Toshiba. The number of masks used for SAQP is the same as for SADP (1 mandrel/core, 1 trim/cut/block), since only pitch-doubled patterns need cutting. The remaining patterns do not need cutting or trimming, since they are patterned through the same initial exposure.
A similar approach to protrusion cutting is the concept of the linking feature. The linking feature is a narrow constriction which separates features when the sidewall spacer is deposited and patterned. Line jogs, possibly track changing, are necessary to establish the linking feature.
Complementary polarity exposures
The method of complementary exposures is another way of reducing mask exposures for multiple patterning. Instead of multiple mask exposures for individual vias, cuts or blocks, two exposures of opposing or complementary polarity are used, so that one exposure removes interior portions of the previous exposure pattern. The overlapped regions of two polygons of opposite polarity do not print, while the non-overlapped regions define locations that print according to the polarity. Neither exposure patterns the target features directly. This approach was also implemented by IMEC as two "keep" masks for the M0A layer in their 7nm SRAM cell.
Self-aligned blocking is currently being targeted for use with SAQP for sub-30 nm pitches. The lines to be cut are divided into two materials, which can be etched selectively. One cut mask only cuts every other line made of one material, while the other cut mask cuts the remaining lines made of the other material.
EUV Multiple Patterning Possibilities
Although EUV has been projected to be the next-generation lithography of choice, it could still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them; a single EUV exposure pattern has difficulty with line end-to-end spacing control.
The existing 0.33 NA EUV tools are challenged below 16 nm half-pitch resolution. Tip-to-tip gaps are problematic for 16 nm dimensions. Consequently, EUV 2D patterning is limited to >32 nm pitch. Recent studies of optimizing the EUV mask features and the illumination shape simultaneously have indicated that different patterns in the same metal layer could require different illuminations. On the other hand, a single exposure only offers a single illumination.
For example, in a cross-pitch source-mask optimization for 7nm node, for 40-48 nm pitch and 32 nm pitch, the quality as determined by the normalized image log slope was insufficient (NILS<2), while only 36 nm pitch was barely satisfactory for bidirectional single exposure.
The underlying situation is that EUV patterns may be split according to different illuminations for different pitches, or different pattern types (e.g., staggered arrays vs. regular arrays). This could apply to line-cutting patterns as well as contact/via layers. It is also likely more than one cut would be needed, even for EUV.
At the 2016 EUVL Workshop, ASML reported that the 0.33 NA NXE EUV tools would not be capable of standard single exposure patterning for the 11-13 nm half-pitch expected at the 5 nm node. A higher NA of 0.55 would allow single exposure EUV patterning of fields which are half the 26 mm x 33 mm standard field size. However, some products, such as NVIDIA's Pascal Tesla P100, will be bisected by the half-field size, and therefore require stitching of two separate exposures. In any case, two half-field scans consume twice as much acceleration/deceleration overhead as a single full-field scan.
Specific Implementations for 2D Contact/Via/Cut Patterns
Since 32 nm node, Intel has applied the above-mentioned self-aligned via approach, which allows two vias separated by a small enough pitch (112.5 nm for Intel 32 nm metal) to be patterned with one resist opening instead of two separate ones. If the vias were separated by less than the single exposure pitch resolution limit, the minimum required number of masks would be reduced, as two separate masks for the originally separated via pair can now be replaced by a single mask for the same pair.
Pairing wires carrying the same signal allows layouts to be more friendly to multiple patterning, by effectively quadrupling the local wire pitch (i.e., from '1'-'0'-'1'-'0'- signal routing to '0'-'1'-'1'-'0'- signal routing). This also enables connecting via pitch to be at least doubled as well, and, in fact, is more compatible with the self-aligned via processing described above.
Merged hole separation by etch shrink
Tokyo Electron Ltd (TEL) was able to resolve two merged contact holes by applying an etch shrink. 31-32 nm contact half-pitch was achieved through this method, with some room to improve process margin.
2D SID Spacer Patterning
The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration. Cuts not requiring tight positioning may be made on this spacer-generated grid.
Triangular Spacer (Honeycomb Structure) Patterning
Samsung recently demonstrated DRAM patterning using a honeycomb structure (HCS) suitable for 20 nm and beyond. Each iteration of spacer patterning triples the density, effectively reducing 2D pitch by a factor of sqrt(3). This is particularly useful for DRAM since the capacitor layer can be fit to a honeycomb structure, making its patterning simpler.
Memory patterns are already patterned by quadruple patterning for NAND and crossed quadruple/double patterning for DRAM. These patterning techniques are self-aligned and do not require custom cutting or trim masks. For 2x-nm DRAM and flash, double patterning techniques should be sufficient.
Current EUV throughput is still more than 3x slower than 193 nm immersion lithography, thus allowing the latter to be extended by multiple patterning. Furthermore, the lack of an EUV pellicle is also prohibitive.
As of 2016, Intel was using SADP for its 10 nm node; however, as of 2017, the 36 nm minimum metal pitch is now being achieved by SAQP. Intel is using triple patterning for some critical layers at its 14 nm node, which is the LELELE approach. Triple patterning is already demonstrated in 10 nm tapeout, and is already an integral part of Samsung's 10 nm process. TSMC is deploying 7 nm in 2017 with multiple patterning; specifically, pitch-splitting, down to 40 nm pitch. Beyond the 5 nm node, multiple patterning, even with EUV assistance, would be economically challenging, since the departure from EUV single exposure would drive up the cost even higher. However, at least down to 12 nm half-pitch, LELE followed by SADP (SID) appears to be a promising approach, using only two masks, and also using the most mature double patterning techniques, LELE and SADP.
|Patterning Method||Normalized Wafer Cost|
Ref.: A. Raley et al., Proc. SPIE 9782, 97820F (2016).
Compared to 193i SADP, EUV SADP cost is dominated by the EUV tool exposure, while the 193i SAQP cost difference is from the added depositions and etches. The processing cost and yield loss at a lithographic tool is expected to be highest in the whole integrated process flow due to the need to move the wafer to specific locations at high speed. EUV further suffers from the shot noise limit, which forces the dose to increase going for successive nodes. On the other hand, depositions and etches process entire wafers at once, without the need for wafer stage motion in the process chamber. In fact, multiple layers may be added under the resist layer for anti-reflection or etch hard-mask purposes, just for conventional single exposure.
Multipatterning for advanced nodes is already underway. There are two styles being used. Pitch splitting such as LELELE triple patterning is preferred for bidirectional layouts, but is harder to scale. Spacer-based patterning typically makes use of 1D-type layouts, but requires additional masks for cutting. Cutting lines to form irregular patterns uses the maximum number of masks. However, minimum pitch lines with dense cut locations contribute to higher capacitance by adding more locations and more area of minimum spacing. 2D patterning is generally preferred, but requires sufficient exposed feature pitch, followed by sufficient splitting or division of the pitch. On the other hand, LELE, LELELE, and SADP (SID) can avoid line cuts, while SATP or SAQP with grid routing can minimize line cuts. SID SADP as described in US Patent 8312394 (Synopsys) offers the 2D flexibility of LELELE, with less mask count and process complexity compared to either SAQP or LELELE.
|Company||Logic Process||Minimum Metal Pitch (MMP)||Contacted Gate Pitch (CGP)||Fin Pitch||MMP Patterning Technique||Production Start|
|Intel||14nm||52 nm||70 nm||42 nm||SADP||2014|
|Intel||10nm||36 nm||54 nm||34 nm||SAQP||end of 2018|
|TSMC||16FF||64 nm||90 nm||48 nm||LELE||2015|
|TSMC||10FF||42 nm||64 nm||36 nm||SADP||2017|
|TSMC||7FF||40 nm||57 nm||SADP||early 2017|
|Samsung||14LP*||64 nm||78 nm||48 nm||LELE||2015|
|Samsung||10LPE||48 nm||64 nm||LELELE||end of 2016|
|Samsung||8LPP||44 nm||64 nm||LELELELE||end of 2018|
|GlobalFoundries||7LP||40 nm||56 nm||30 nm||SADP||2018|
From a lithographic quality point of view, pitch quartering with 193 nm immersion is better than EUV single exposure. For example, 18 nm half-pitch with 0.33 NA EUV has k1=0.44, while 4x18=72 nm half-pitch with 1.35 NA immersion gives k1=0.50. The ≈14% advantage is always maintained across target pitch. The difficulty increases faster as k1 drops below 0.35. On the other hand, multiple passes would present another difficulty for quadruple patterning. Properly shaping the mandrel is not trivial. Long lines running in one direction require the most cuts; a cut exposure and mask is needed for every path turn. In contrast, spacer patterns with path turns already included do not require cutting if they are used for encapsulating metal.
As the number of masks for a given layer increases, the cost for patterning that layer also increases. It is especially severe when a layer previously requiring only one mask now requires two masks; in this case the cost may roughly be expected to be doubled. On the other hand, the reduced device area from the reduced pitch allows the cost per device to be reduced. The larger pitch reduction allows a larger reduction of cost per device, which counters the effect of increasing mask count.
IMEC has recently studied 7nm scenarios where the pitch in one direction, usually the gate pitch, is larger than the pitch in the perpendicular direction, usually the minimum metal pitch. Such scenarios are advantageous in preventing aggressive increases in mask count when the larger pitch requires SADP instead of SAQP.
The mask cost strongly benefits from the use of multiple patterning. The EUV single exposure mask has smaller features which take much longer to write than the immersion mask. Even though mask features are 4x larger than wafer features, the number of shots is exponentially increased for much smaller features. Furthermore, the sub-100 nm features on the mask are also much harder to pattern, with absorber heights ≈70 nm.
|WPH (wafers per hour)||85||85||275||275|
|WPM (wafers per month)||257,040||128,520||2,138,400||1,069,200|
Note: WPM = WPH * # tools * uptime / # passes * 24 hrs/day * 30 days/month. Normalized WPM = WPM/(WPM for EUV 1 pass)
Multiple patterning with immersion scanners can be expected to have higher wafer productivity than EUV, even with as many as 4 passes per layer, due to faster wafer exposure throughput (WPH), a larger number of tools being available, and higher uptime.
Multiple Patterning Specific Issues
|Overlay||between 1st and 2nd exposures, especially where stitching||among all three exposures, especially where stitching||between core and cut exposures||between core and cut exposures|
|Exposed feature width||(1) 1st exposure (2) 2nd exposure||(1) 1st exposure (2) 2nd exposure (3) 3rd exposure||core feature||(1) core feature (2) cut shape|
|Feature slimming target width||1/4 exposure pitch||1/6 exposure pitch||1/4 core pitch||1/8 core pitch|
|Spacer width||N/A||N/A||1 spacer||(1) 1st spacer (2) 2nd spacer|
Multiple patterning entails the use of many processing steps to form a patterned layer, where conventionally only one lithographic exposure, one deposition sequence and one etch sequence would be sufficient. Consequently, there are more sources of variations and possible yield loss in multiple patterning. Where more than one exposure is involved, e.g., LELE or cut exposures for SAQP, the alignment between the exposures must be sufficiently tight. Current overlay capabilities are ≈0.6 nm for exposures of equal density (e.g., LELE) and ≈2.0 nm for dense lines vs. cuts/vias (e.g., SADP or SAQP) on dedicated or matched tools. In addition, each exposure must still meet specified width targets. Where spacers are involved, the width of the spacer is dependent on the initial deposition as well as the subsequent etching duration. Where more than one spacer is involved, each spacer may introduce its own width variation.
The evolution of multiple patterning is being considered in parallel with the emergence of EUV lithography. While EUV lithography satisfies 10-20 nm resolution by basic optical considerations, the occurrence of stochastic defects as well as other infrastructure gaps and throughput considerations prevent its adoption currently. Consequently, 7nm tapeouts have largely proceeded without EUV. In other words, the multiple patterning is not prohibitive, but more like a nuisance and growing expense. 5nm may be expected in 2020, with the evolution of multiple patterning and status of EUV considered at that time.
7nm and 5nm FinFETs
Self-aligned quadruple patterning is already the established process to be used for patterning fins for 7 nm and 5 nm FinFETs. With SAQP, each patterning step gives a critical dimension uniformity (CDU) value in the sub-nanometer range (3 sigma). Among the four logic/foundry manufacturers, only Intel is applying SAQP to the metal layers, as of 2017.
Reduced cell heights (fewer tracks per cell)
Recent advances in design-technology co-optimization have led to SAQP-friendly layouts, which do not lead to dramatic mask count increases. Such advances also include reductions of cell height through the use of fewer metal tracks within the cell. The new cell designs result in fewer cut locations and via connections within the cell, while reducing cell area. Essentially, the SAQP metal layers are horizontal lines with at most one connection in the middle of the cell, so that only one block/cut mask is needed without changing lithography tool. Likewise, only diagonally adjacent vias are placed on different masks; vias for every other vertical metal line (corresponding to two gate pitches) may be placed on the same mask.
Like NAND Flash, DRAM has also made regular use of multiple patterning. Even though the active areas form a two-dimensional array, one cut mask is sufficient for 20 nm. Furthermore, the cut mask may be simultaneously used for patterning the periphery, and thus would not count as an extra mask. However, for 14-18 nm, one additional cut mask would be necessary for dividing the active areas. Samsung has already started manufacturing the 18 nm DRAM.
3D NAND Flash
3D NAND flash may use SADP for some layers. While it does not scale so aggressively laterally, the use of string stacking in 3D NAND would imply the use of multiple patterning (litho-etch style) to pattern the vertical channels.
Mixed patterning methods
Multiple patterning may evolve toward a combination of multiple exposures, spacer patterning, and/or EUV. Especially with tip-to-tip scaling being difficult in a single exposure on current EUV tools, a line-cutting approach may be necessary.
|Lines||Grid intersecting lines||Selected grid locations for cuts/vias|
multiple DUV exposures
|EUV 2nd exposure;
overlaid spacer grid (DUV 2nd exposure);
multiple DUV exposures
|(included in EUV 2nd exposure);|
overlaid spacer grid location selection (DUV 3rd exposure);
(included in multiple DUV exposures)
For line patterning, SADP/SAQP could have the advantage over the EUV exposure, due to cost and maturity of the former approach and stochastic missing or bridging feature issues of the latter. For grid location patterning, a single DUV exposure following grid formation also has the cost and maturity advantages (e.g., immersion lithography may not even be necessary for the spacer patterning in some cases) and no stochastic concerns associated with EUV. Grid location selection has an advantage over direct point cutting because the latter is sensitive to overlay.
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