Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.
Although EUV has been projected to be the next-generation lithography of choice, it would still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them. It is also likely more than one cut would be needed, even for EUV.
- 1 Pitch Splitting
- 2 Sidewall Image Transfer
- 3 Self-aligned contact/via patterning
- 4 Published approaches
- 5 Multiple Patterning vs. EUV
- 6 20nm to 14nm nodes (28-40 nm Half-pitch): Litho-Etch-Litho-Etch (LELE)
- 7 14nm to 10nm nodes (20-28 nm Half-pitch): Self-Aligned Spacer
- 8 Beyond 10nm node (Sub-20 nm Half-pitch): Quadruple Patterning
- 9 Reduction of mask counts
- 10 Specific Implementations
- 11 Industrial adoption
- 12 References
The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.
Sidewall Image Transfer
As pitch splitting has become more difficult due to possible differences in feature positions between different exposed parts, sidewall image transfer (SIT) has become more recognized as the necessary approach. The SIT approach typically requires a spacer layer to be formed on an etched feature's sidewall. If this spacer corresponds to a conducting feature, then ultimately it must be cut at no less than two locations to separate the feature into two or more conducting lines as typically expected. On the other hand, if the spacer corresponds to a dielectric feature, cutting would not be necessary. The prediction of how many cuts would be needed for advanced logic patterns has been a large technical challenge. Many approaches for spacer patterning have been published (some listed below), all targeting the improved management (and reduction) of the cuts.
Self-aligned contact/via patterning
Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and has been extended to patterning of active areas (see "Crossed self-aligned patterning" below). It is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.
|Minimum Exposures||Metal Half-pitch||Node||References|
|36-45 nm||32/28/22 nm|||
|26-35 nm||20/16/14 nm|||
||17-26 nm||10 nm|||
|15-18 nm||7 nm|||
193i (full-field) + 2 EUV(High-NA half-fields)
|11-13 nm||5 nm|||
The above approaches are for random logic patterns. Memory patterns are already patterned by quadruple patterning for NAND and crossed quadruple/double patterning for DRAM. These patterning techniques are self-aligned and do not require custom cutting or trim masks.
Multiple Patterning vs. EUV
There have been numerous concerns that multiple patterning diminishes or even reverses the node-to-node cost reduction expected with Moore's Law. One or two 193i exposures can scale down to 7 nm node. Extra cost at 7 nm node is anticipated from replacement of a single 193i exposure by EUV or two 193i exposures. EUV is more expensive than three 193i exposures, considering the throughput. Moreover, EUV is more liable to print smaller mask defects not resolvable by 193i. 5 nm node adds even more exposure costs.
20nm to 14nm nodes (28-40 nm Half-pitch): Litho-Etch-Litho-Etch (LELE)
A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.
A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography .
This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.
A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.
A variation on this approach which eliminates the first hardmask etch is resist freezing, which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method, where the freezing is accomplished by surface hardening of the first resist layer.
14nm to 10nm nodes (20-28 nm Half-pitch): Self-Aligned Spacer
In spacer patterning, a spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Doubled Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.
The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes. For example, two iterations of SADP leads to quartering of the pitch or quadrupling of features within the original pitch. Hence, this is often referred to as Self-Aligned Quadruple Patterning (SAQP). This conveniently avoids the serious issue of overlay between successive exposures. The spacer lithography technique has most frequently been applied in patterning fins for FinFETs.
As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.
The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other. Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking.
The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.
Spacer-Is-Dielectric (SID) Patterning
In the original spacer-based technique, the spacers defined conducting features which needed to be cut to avoid forming loops. In the spacer-is-dielectric (SID) approach, the spacers define dielectric spaces between conducting features, and so no longer need cuts. Instead the mandrel definition becomes more strategic in the layout, and there is no longer a preference for 1D line-like features. The SID approach has gained popularity due to its flexibility with minimal mask count.
Beyond 10nm node (Sub-20 nm Half-pitch): Quadruple Patterning
Beyond double (2X) patterning, the most frequently published multiple patterning methodology is the repeated spacer approach, which can be practiced in many forms. A multilayer-on-topography spacer-type approach also offers some flexibility.
EUV multiple patterning at 7nm and beyond
In November 2014, ASML revealed that the 7 nm node (16 nm half-pitch), the first node for possible EUV use, would still require double patterning, to an even greater extent than immersion lithography did at 20 nm node. This double patterning can be of the EUV+EUV type, but is more likely to be the complementary combination of 193i+EUV, due to the lower cost of 193i compared to EUV.
High NA (>0.5) EUV is expected to be needed for the 5 nm node (11 nm half-pitch). Such tools would change the field size from the conventional 26 mm x 33 mm to 26 mm x 16.5 mm, as the mask demagnification in the direction corresponding to 16.5 mm field width is doubled from 4x to 8x. Hence, the EUV mask needs to have two exposures (one for each half of a conventional 4x 26 mm x 33 mm field) to match the single exposure field size used by immersion lithography tools.
If the SID approach is applied after SADP, quadruple patterning can be achieved without additional cuts beyond that required for double patterning. The flexibility comes from having the spacer not define the metallic features, since they are normally loops which need to be cut. By trimming the spacers and having the spacer define dielectric locations, separate line cutting exposures can be minimized, even possibly eliminated. Additional resolution is achieved by conversion into the SAQP approach by having the metal-patterning mandrels themselves defined by SADP. A double-patterned metal pattern layout can turn into a quadruple-patterned layout, without additional masks, due to the final spacer loop being dielectric. In this way, the cost effectiveness of multiple patterning even for flexible 2D layouts is improved with the use of (up to) two masks for SAQP down to ~11-12 nm half-pitch. EUV thus far has not shown 2D flexibility for 16 nm half-pitch (7 nm node) and would therefore require the same number of mask exposures as 193 nm immersion in this case. SAQP may be extended to SAOP by applying an additional spacer. The benefit of SID in extending multiple patterning may be generalized, noting that a 2N-patterned metal pattern layout can turn into a 4N-patterned layout, without additional masks, due to the final spacer loop being dielectric.
Directed self-assembly (DSA)
As of 2010, much progress was reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy). The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Nevertheless, the timing for sub-20 nm node ~2013 is currently being targeted. Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders. However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.
The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter. A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)−1/2, where a is the statistical polymer chain length. Moreover, χN>>10 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π2)1/3aN2/3χ1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.
Reduction of mask counts
In order to avoid the increase of mask count from more cuts required for smaller patterns, a number of approaches have been published.
Sidewall profile modulation (SPIMM)
IBM had pioneered a couple of techniques for removing sidewall spacers in some locations while leaving them intact at others. However, these locations may not necessarily be paired. The Sidewall Profile Inclination Modulation Mask (SPIMM) technique was proposed in 2013 by Frederick Chen of ITRI as a means to reduce the number of exposures for spacer-defined or possibly DSA-defined double patterning or multiple patterning even for arbitrary, non-arrayed patterns. A dose gradient, such as from a subresolution feature adjacent a feature edge, is transferred to form a more sloped sidewall profile, which allows the deposited spacer patterning to be interrupted locally. A developable BARC process is a suitable approach, due to its reduced exposure contrast. Alternatively, the sloped sidewall profile can be formed in the resist directly. It has been shown that the placement of the sub-resolution assist feature (SRAF) can affect the resist profile.
SMIC recently developed a double patterning method where a negative-tone developed photoresist is coated over a positive-tone developed photoresist. The two photoresists respond to different dose thresholds, and furthermore, after the upper photoresist is negatively developed, the lower photoresist is etched using the upper photoresist as etch mask. The lower photoresist is subsequently positively developed. This results in a double-patterned structure similar to the spacer patterning method but not requiring the spacer deposition. It is also a single exposure double patterning technique, which allows additional cost reduction.
The number of masks may be reduced with the use of DSA due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure. Alternatively, the cut pattern itself may be generated as a DSA step.
The most aggressive cut reduction which may be targeted for 5 nm node is the gridded cut approach. The cut locations are a selected subset of a grid, patterned by DSA or repeated spacer patterning, with the selection exposure being relatively easy due to many cut pitches being covered at once.
SAQP Grid Routing
Currently, the smallest number of masks for SAQP may be achieved by the grid routing method described by Toshiba and Tokyo Institute of Technology in 2015.
The number of masks used is the same as for SADP (1 mandrel/core, 1 trim/cut), since only the tertiary loop patterns need cutting. The mandrel and passive secondary patterns do not need cutting or trimming, since they are patterned with a single exposure.
Merged hole separation by etch shrink
2D SID Spacer Patterning
The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration.
Triangular Spacer (Honeycomb Structure) Patterning
Samsung recently demonstrated DRAM patterning using a honeycomb structure (HCS) suitable for 20 nm and beyond. Each iteration of spacer patterning triples the density, effectively redycing 2D pitch by a factor of sqrt(3).
In a press release, Samsung also announced that its 14 nm FinFET development relied on working with partner Mentor to "deal with the complexities of multi-patterning lithography."
Intel reported in 2013 that it would be using pitch quartering, i.e., SAQP, for its 10 nm node (15-22 nm half-pitch), instead of EUV. However, Intel's 10 nm introduction has apparently been delayed from 2015 to 2017.
Triple patterning is already established for 14 nm and 10 nm nodes. Any self-aligned multiple patterning followed by two trimming or cutting exposures (SAQP-LELE) for 7 nm and 5 nm nodes, effectively extends triple patterning to these nodes. Fewer cuts, e.g., enabled by SID or self-aligned triple patterning (SATP), would offer even more cost-effective scalability.
The 7 nm node requires capability for 32 nm pitch. Double patterning is insufficient; at least triple patterning is necessary. 5 nm node would require 22 nm pitch, mandating the use of quadruple patterning.
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