Die shot of NEC V60 microprocessor
Name "V60 D70616" in bottom center
|Max. CPU clock rate||V60: 16 MHz|
V70: 20/25 MHz
V80: 25/33 MHz
AFPP: 20 MHz
|Min. feature size||V60: 1.5/1.2 μm|
V70: 1.5/1.2 μm
V80: 0.8 μm
AFPP: 1.2 μm
|Instruction set||NEC V60-V80|
|L1 cache||V80: 1K/1K|
|Data width||V60: 16 (int. 32)|
|Address width||V60: 24 (int. 32)|
|Virtual address width||32 Linear|
|Product code name(s)|
NEC V60 is a CISC microprocessor once manufactured by NEC started in 1986. It has MMU, and RTOS supports both for Unix-based user-application-oriented systems and for I‑TRON based hardware-control-oriented embedded systems. This article also describes V70 and V80 because these have the same ISA as V60. In addition, dedicated co-FPP, multi-cpu lockstep fault-tolerant mechanism named FRM, development tools including Ada certified system MV‑4000, and ICE are described. At last, their successor the V800 Series product families are briefly introduced.
V60/V70/V80's application covered much wide area, including: circuit switching telephone exchanges, minicomputers, aerospace guidance systems, word processors, industrial computers, and various game arcades.
Nowadays, CPU simulator software has been kept providing by the MAME development team, to emulate old games for enthusiasts. The latest open-source code is available from GitHub repository (<mamedev/mame></src/devices/cpu/v60/>).
- 1 Introduction
- 2 Overview
- 3 V60
- 4 V70
- 5 V80
- 6 AFPP (co‑FPP)
- 7 Hardware Architecture
- 8 Operating Systems
- 9 Development Tools
- 10 In-Circuit Emulator
- 11 Fading and Successors
- 12 Emulator (CPU Simulator) Software
- 13 See also
- 14 References
- 15 External links
Based on a relatively traditional design at that moment, indeed it was a radical divorcing from NEC's previous 16-bit V–Series; the V20-V50. Those were based on the Intel 8086 model. But V60 still retained the ability to emulate V20/V30.:§10 According to NEC's documentation, this computer architectural change was made due to the increasing demands for, and the diversity of, high-level programming languages. Such trend called for a processor both with performance; doubling buses width to 32 bits, and with flexibility; having large numbers of general-purpose registers. These were a part of common features of Reduced Instruction Set Computer. This transition from CISC to RISC brought much benefits to the emerging markets — at that moment.
But today, both of two Silicon Valley born RISCs are pressed, instead Intel's x86 has been main stream for these decades. The reason is, though x86 has CISC ISA, 80486 internally adopts RISC features. According to Pat Gelsinger's word, binary backward compatibility for the legacy software assets is much important than ISA change.
The V60 (μPD70616) /.mu.PD70616/, however, staid in CISC features. Its manual describes them as mainframe-computer-based fully orthogonal instruction set, in other words, Complex Instruction Set Computer, which comprises; non-uniform length instructions, memory-to-memory operations including string manipulation, and fairly complex operand addressing schemes.
The V60 has 32 bits internal buses although it has externally narrower 16 bits data and 24 bits address buses. In addition, V60 has 32 of 32-bit general-purpose registers.:§1 Its basic architecture is inherited to the following models. The V70 (μPD70632) has 32 bits external buses, released in 1987. Launched in 1989, the V80 (μPD70832) is the culmination of the series; having on-chip caches, having a branch predictor, and less reliance on microcode for complex operations.
Because the V60/V70 has been used for various Japanese game arcades, their instruction set architecture is still surviving as the CPU simulator, called MAME, Multiple Arcade Machine Emulator, for this niche. The latest open-source code is available from GitHub repository (<mamedev/mame></src/devices/cpu/v60/>).
All three processors has the synchronous multiple modular lockstep mechanism named FRM (Functional Redundancy Monitoring), which enables fault-tolerant computer systems. It requires plural of devices of the same model, then one of them becomes the "master mode," while the other devices listen to the master device in the "checker mode." If two or more devices arise different result via their "fault output" pins simultaneously, the majority voting decision can be made by external circuits. In addition, recovery method, either with roll-back by "retry" or with roll-forward by "exception" for the instruction which is detected mismatch, can be selected via an external pin.:§11:§3-229, 266
|BMODE (FRM)||Input||Select the normal bus (master) mode or FRM operating (checker) mode|
|BLOCK (MSMAT)||Output||Master output requesting bus lock, i.e. freezing bus operation|
Checker output indicating a mismatch has been detected
|BFREZ||Input||Assertion for freezing bus operation|
|RT/EP||Input||Selecting input for "roll-back by retry" or "roll-forward by exception"|
The work on V60 processor began in 1982 under the leadership of Yoichi Yano. About 250 engineers participated and the V60 (μPD70616) debuted in February 1986. It had a six-stage pipeline, built-in memory management unit and floating-point arithmetic. It was manufactured in 1.5 μm on a two-layer aluminum metal CMOS process using 375,000 transistors on a 13.9 × 13.8 mm2 die. It operated at 5 V and was initially packaged in a 68-pin PGA. The first version ran at 16 MHz and attained 3.5 MIPS. Its sample price at launch was set to ¥100,000 ($588.23). It entered full-scale production in August 1986.
Sega employed this processor for the most of its arcade game sets in the 1990s; both the Sega System 32 and the Sega Model 1 architectures used V60 for their main CPU. (The latter one used lower-cost variant μPD70615 /.mu.PD70615/, which doesn't implement V20/V30 emulation and FRM. ) The V60 was also used for the main CPU in the SSV arcade architecture—so named because it was developed together by Seta, Sammy, and Visco. Sega originally considered using a 16 MHz V60 as the basis for its Sega Saturn console, but after receiving the word, that the PlayStation employed a MIPS R3000A at 33.8 MHz processor, instead chose the dual-SH-2 design for the eventual production model.
In 1988, NEC released a kit called PS98-145-HMW for Unix enthusiasts. The kit contained a V60 processor board that could be plugged into selected models of the PC-9800 computer series and a '15 8"-floppy disks distribution' of their UNIX System V port, the PC-UX/V Rel 2.0 (V60). The suggested retail price for this kit was 450,000 Yen. NEC group companies themselves intensively employed V60 processor. Their telephone circuit switcher (exchanger), which was one of the first intended target, used V60. In 1991, they expanded word processor products line, named "Bungou Mini" (文豪ミニ in Japanese) series 5SX, 7SX, and 7SD, with a V60 for fast outline font processing, while the main system processor was a 16 MHz NEC V33 ("high speed outline font smoothing" TV CM on YouTube). In addition, V60 has microcode variants for NEC's minicomputer MS-4100 Series, which was the fastest one in Japan at that moment.
The V70 (μPD70632) /.mu.PD70632/ improved on V60 by widening external buses to 32 bits, then both internal and external buses became 32 bits width. It was also manufactured in a 1.5 μm with two-metal layer process. Its 14.35 × 14.24 mm2 die had 385,000 transistors and was packaged in a 132-pin ceramic PGA. Its MMU had support for demand paging. Its floating-point unit claimed IEEE 754 compliance. The 20 MHz version attained a peak performance of 6.6 MIPS and was priced at launch in August 1987 at ¥100,000 ($719.42). Initial production capacity was 20,000 units monthly. A later report describes it as fabricated in 1.2-micrometer CMOS and 12.23 × 12.32 mm2 die. The V70 had a two-cycle non-pipeline (T1-T2) external bus system, whereas that of the V60 operated at 3 or 4 cycles (T1-T3/T4). Of course, the internal units were pipelined.
The "aerospace-spec" (JAXA formerly NASDA qualified EEE grade) variant of V70, running with RX616, was embedded in the main control module called Guidance Control Computer by JAXA into the H‑IIA carrier rockets, and satellites such as Akatsuki (Venus Climate Orbiter) and Kibo (ISS module). It had been used until their replacement in 2013 flight 22 with the 64-bit microprocessor HR5000, which is based on MIPS64-5Kf architecture, fabricated by HIREC. The H‑IIA type launch vehicles deployed domestically in Japan, although JAXA called for satellites as its payload from the foreign countries. As is described in JAXA's LSI (MPU/ASIC) roadmap, this V70 variant is "32bit MPU (H32/V70)" which development term, probably including QT phase, was "from the middle of 1980's to early 1990's." In addition, the HR5000 is "64bit MPU (25MHz)," which development is completed around 2011. Then V70 was retired.:9
"Space Environment Data Acquisition" for the V70 was done by Kibo-ISS exposed facility.
|Item||Part No.||SEE (Single Event Effect)
|SEU (Single Event Upset)
SEL (Single Event Latch-up)
The V80 (μPD70832) /.mu.PD70832/ was launched in the spring of 1989. By incorporating on-chip caches and a branch predictor, it was declared NEC's 486 by Computer Business Review. The performance of V80 was two to four times than that of V70, depending on application. For example, compared with V70, the V80 had a 32-bit hardware multiplier to reduce integer multiplication cycles to 9 from 23. (For more detailed differences, see hardware architecture section below.) The V80 was manufactured in 0.8-micrometer CMOS process with a die area of 14.49 × 15.47 mm2 consisting of 980,000 transistors. It was packaged in a 280-pin PGA, and operated at 25 and 33 MHz with claimed peak performance of 12.5 and 16.5 MIPS, respectively. V80 had separated 1 KB on-die cache both for instructions and for data, and had 64-entry branch predictor; the performance gain, attributed to the latter, was about 5%. The launch prices of V80 were cited as equivalent to $1200 for the 33 MHz model and $960 for the 25 MHz model. Supposedly a 45 MHz model was scheduled for 1990, but did not materialize.
The AFPP (μPD72691) /.mu.PD72691/ is a co-processor for floating point arithmetic operations. The name stands for Advanced Floating Point Processor as is described in NEC's data sheet. The V60/V70/V80 themselves can perform floating point arithmetic, but they are very slow because of microcode operations without dedicated hardware. In 1989, to compensate V60/V70/V80 for their fairly weak floating point performance, NEC launched the 80-bit floating point co-processor; for 32-bit single precision, for 64-bit double precision, and for 80-bit extended precision IEEE 754 format operations. This chip claimed 6.7 MFLOPS in the vector-matrix multiplication, operating at 20 MHz. It was fabricated in 1.2-micrometer double-metal layer CMOS process containing 433,000 transistors on an 11.6 × 14.9 mm2 die. It was packaged in a 68-pin PGA. This co-processor connected to V80 via the dedicated bus. But in case of connecting to V60 and V70, it shared their main buses, which scenario diminished their peak performance.
V60/V70/V80 shared the basic architecture. They had thirty-two 32-bit general-purpose registers, although the last three of them were commonly used as stack pointer, frame pointer, and argument pointer, those were well matched with high level language compilers' calling conventions. The V60 and V70 had a 119-instruction set, slightly extended to 123 instructions for the V80. The instructions have non-uniform length between one and 22 bytes, and they take two operands, both of which can be memory locations. After studying the V60's reference manual, Paul Vixie described it as "a very VAX-ish arch, with a V20/V30 emulation mode (which, if you recall, means it can run Intel 8086/8088 software)".
V60-V80 had a built-in MMU that divide the 4 GB virtual address space into in four 1-GB sections, each section further divided in 1,024 1-MB areas, each area composed of 256 4-KB pages. On the V60/V70 four registers (ATBR0 to ATBR3) store section pointers on the processor, but the area tables entries (ATE) and page tables entries (PTE) are stored into off-chip RAM. The V80 merged the ATE and ATBR registers, which are both on-chip with only the PTE entries stored into external RAM, allowing for a faster execution of TLB misses by eliminating one memory read.
The TLBs on the V60/70 are 16-entry fully associative with replacement done by microcode. The V80 in contrast has a 64-entry 2-way set associative TLB with replacement done in hardware. TLB replacement took 58 cycles in the V70 and also disrupted the pipelined execution of other instructions. On the V80 a TLB replacement took only 6/11 cycles depending if the page was in the same area or not; pipeline disruption no longer occurred in V80 because of the separate TLB replacement hardware unit which operated in parallel to the rest of the processor.
All three processors used the same protection mechanism with 4 execution levels (set via a program status word), with ring 0 being the privileged level that could access a special set of privileged registers on the processors.
All three models supported a triple-mode redundancy configuration with three CPUs used in a byzantine fault tolerance scheme with bus freeze, instruction retry, and chip replacement signals. The V80 also added parity signals to its data and address buses.
String operations were implemented in microcode in the V60/V70, but aided by hardware Data Control Unit in the V80, running at full bus speed. This made string operations about five times faster in the V80.
All floating point operations are largely implemented in microcode across the family and thus and are fairly slow. On the V60/V70 the 32-bit floating point operations took 120/116/137 cycles for addition/multiplication/division, while the corresponding 64-bit floating point operations took 178/270/590 cycles. The V80 had some limited hardware assist for parts of the floating point operations, e.g. decomposition into sign, exponent and mantissa, thus its floating point unit was claimed up to 3 times as effective as the one of the V70, with 32-bit operations taking 36/44/74 cycles while 64-bit floating point operations taking 75/110/533 cycles on the V80 (again, for addition/multiplication/division).
Unix (non-real-time and real-time)
NEC ported several variants of Unix to its V60/V70/V80 processors for user-application-oriented systems, including real-time ones. The first flavor of NEC's UNIX System V port for V60 was called PC-UX/V Rel 2.0 (V60). (also refer to external link photos below, much interesting) NEC also developed a variant for V60/V70/V80 with a focus on real-time operation called Real-time UNIX RX-UX 832. It has double layered kernel structure, and all the kernel call of Unix issues task to the real-time kernel. The multiprocessor version of RX-UX 832 was also developed, and was named MUSTARD (A Multiprocessor Unix for Embedded Real-Time Systems). The MUSTARD-powered computer prototype used eight V70 processors. It utilize FRM function, and can configure and change the structure of master and checker upon request. (Google Books)
For hardware-control-oriented embedded systemss, the I‑TRON based real-time operating system, named RX616, was implemented by NEC for the V60/V70. The 32-bit RX616 was a continuous fork from the 16-bit RX116, which was for the V20-V50.
CP/M and DOS (legacy 16-bit)
The V60 could also run CP/M and DOS programs (ported from the V20-V50 series) using V20/V30 emulation mode. According to a 1991 article in InfoWorld, Digital Research was working on a version of Concurrent DOS for the V60 at some point, but this was never released as the V60/V70 processors were not imported in the US for use in PC clones.
C/C++ cross compilers
Regarding the development tool kit and IDE, NEC had its own C compiler the PKG70616; "Software Generation tool package for V60/V70." In addition, GHS (Green Hills Software) made its native mode C compiler (MULTI), and MetaWare, Inc. (currently Synopsys, via ARC International) made one for V20/V30 emulation mode, i.e. 8086 model, called High C/C++.:acknowledgement Cygnus Solutions (currently Red Hat) also ported GCC in a part of EGCS fork, but it seems not to be public.
As of 2018, the machine directory necv70 is still kept alive in the newlib C language libraries (libc.a and libm.a) by RedHat. Its home page is https://sourceware.org/newlib/. Recent maintenance seems to be done on <2016-12-23>. The latest source code is available from its git repository <newlib/libc/machine/necv70>. The assembler source code <setjump.S> is truly the mnemonic of V70.
MV-4100 Ada 83 certified system
The Ada 83 certified platform system was named MV‑4000, sometimes notified as MV4000. This certification was done with "the target" system, that utilized Real-time UNIX RX-UX 832 OS running on the VMEbus (IEEE 1014) based system, a V70 processor board plugged in. "The host" of the cross compiler was the NEC Engineering Work Station EWS 4800. Its "host os" EWS-US/V was also UNIX System V based.
The certification status is issued as the ADA YEAR BOOK. The status of MV‑4000 (notified as MV4000) can be found such as 1994, and 1995 revision.
Ada 83 validation status by AETECH, Inc.
NOTE: In accordance with the Ada Validation Procedures (Version 5.0), certificates will no longer be issued for Ada 83 compilers. Testing may be performed by an Ada Conformity Assessment Laboratory (ACAL) for specific procurement requirements, and the ACAA will issue a letter affirming such testing, but no certificates will be issued. All validation certificates ever issued for testing under Version 1.11 of the ACVC test suite expired on 31 March 1998.
|System Name||Certificate Number||Compiler Type||HOST Machine||HOST OS||TARGET Machine||TARGET OS|
|NEC Ada Compiler System for EWS-UX/V to V70/RX-UX832, Version 1.0||910918S1.11217||Base||NEC EWS4800/60||EWS-UX/V R8.1||NEC MV4000||RX-UX832 V1.6|
|NEC Ada Compiler System for EWS-UX/V(Release 4.0) to V70/RX-UX832 Version Release 4.1 (4.6.4)||910918S1.11217||Derived||EWS4800 Superstation RISC Series||EWS-UX/V(R4.0) R6.2||NEC MV4000||RX-UX832 V1.63|
|MV‑4000 Features |
|System bus: IEEE1014 D1.2/IEC821 Rev C.1 (8-slot)|
|Expansion bus: IEC822 Rev C or V70 cache bus (6-slot)|
|Built-in 100M byte (formatted) 3.5-inch SCSI hard disk|
|Built-in 1M-byte 3.5-inch floppy disk drive 1|
|Expansion SCSI (1 ch)|
|EMI evaluation: VCCI - 1 kind|
Evaluation board kits
NEC released some of plug-in type evaluation board kits for V60/V70.
|EBIBM-7061UNX||V60 coprocessor slave board with Unix for PC-XT/AT||w/ PC-UX/V Rel 2.0 (V60)|
|PS98-145-HMW||V60 coprocessor slave board with Unix for NEC PC-9801||w/ PC-UX/V Rel 2.0 (V60)|
|EBIBM-70616SBC||V60 single board computer for Multibus I|
|A part of MV-4000||V70 single board computer for VMEbus||Ada 83 certified|
On-chip software debug support
NEC had its own full (non-ROM and non-JTAG) probe-based in-circuit emulator; the IE-V60 because V60/V70 themselves had emulator-chip capabilities. NEC described it as "user friendly software debug function." In fact, they have various trapping exceptions, such as data read (or write) to the user specified address, and 2 break-points simultaneously. Section 9 
External bus status pins
External bus system also indicates its bus status with 3 bits of status pins, such as the first instruction fetch after branch, continuous instruction fetch, TLB data access, single data access, sequential data access. Section 6.1, p. 114 
|011||Instruction fetch after branch|
|101||"TLB" data access|
|100||"System base (interrupt & exception vector) table" data access|
|011||Single data access|
|010||Short-path data access (Skipped address by read-after-write)|
|001||Sequential data access|
Debugging with V80
These software and hardware debugging functions were also built on the V80, but it did not have in-circuit emulator. Probably because it succeeded much fruits from V60/V70, such as real-time UNIX RX-UX 832 and real-time I‑TRON RX616. Think, if once Unix boots up, who needs in-circuit emulator both for developing device driver and for developing application software. What developer need is a C compiler, self as well as cross, and the screen debugger, working with the target device, such as GDB-Tk.
The IE-V60 was the first in-circuit emulator for V60 manufactured by NEC. It also had PROM programmer function. Section 9.4, p. 205
Hewlett Packard (currently Keysight) offered a probing-pod-based In-circuit emulation hardware for the V70, built on their HP 64700 Series systems, successor of HP 64000 Series (detailed description is available within Wikipedia, with graphical image), more precisely the HP 64758 emulated the V70. It enables trace function like a logic analyzer. This test equipment also displays disassembled instruction level source code automatically; with trace data display; without any object file. And displays high-level language source code if user provide the source code and the object file, which is compiled with DWARF information. Interface for V60 (10339G) is also listed in the catalog. But long probing-pod cable required "special grade qualified" devices, i.e. high speed grade V70.
HP 64758: Main units, sub-nits, and hosted interface
|64758A||V70 20 MHz Emulator 512KB of Emul. mem.|
|64758B||V70 20MHZ Emulator 1MB of Emulation mem.|
|64758G||V70 20 MHz emulation subsystem 512KB|
|64758H||V70 20 MHz emulation subsystem 1MB|
|64758S||V70(uPD70632) Hosted User Interface|
|64879L||V70 Assembler/Linker Single User License|
|64879M||V70 Assembler/Linker Media & Manuals|
|64879U||V70 Assembler/Linker Multi-user license|
|B3068B||V70 Graphical Hosted User Interface|
|10339G||NEC V60 INTERFACE|
|E2407A||NEC V70 INTERFACE|
Fading and Successors
Strategic failure of the V80 microarchitecture
In its development phase, the V80 was thought as the same performance chip as the Intel 80486. But, as the result, they became much different features. The internal execution for each instruction of the V80 needed at least 2 cycles, while that of i486 was 1. The internal pipeline of the V80 seemed buffered A-synchronous, but that of i486 was synchronous. In other words, the internal microarchitecture of V80 was CISC, but that of i486 was RISC. Both of their ISA had long non-uniform CISC instructions, so i486 adopted wider 128-bit internal cache memory, while that of V80 was 32-bit width. This difference can be seen on their die photos. This strategic failure was fatal from the performance point of view, but NEC did not change its design. NEC might be able to throw away its physical design, and to reconsider in register-transfer level as soon as possible, but it did not.
The V60-V80 architecture did not enjoy much commercial success.
The V60, V70, and V80 were listed in 1989 and 1990 NEC catalogs in their PGA packaging. A NEC catalog from 1995 still listed the V60 and V70 (not only in their PGA version but also in a QFP packaging, and also included a low-cost variant of the V60 named μPD70615, which eliminated V20/V30 emulation and FRM function), alongside their assorted chipset, but the V80 is not offered in this catalog. The 1999 edition of the same catalog no longer has any V60-V80 products.
The V800 Series
In 1992, NEC launched new model, the V800 Series 32-bit microcontroller, but it does not have MMU (Memory Management Unit). Those were much different from CISC, but RISC-based architecture, inspired by the Intel i960, MIPS architecture, and other RISC processor instructions, such as JARL (Jump and Register Link), and load/store architecture.
At this moment, all the huge software assets of the V60/V70, like real-time Unix, were lost and never returned to their successors. The scenario Intel circumvents.
V820 (μPD70742) was a simple variant of V810 (μPD70732) with peripherals. The #4 seems to be skipped (see page 58 ), probably because of Japanese tetraphobia. One Japanese pronunciation of "4" means "death." So the successors well avoid the Death-watch; Shi-ban (#4; Shi-ban) Bug (死番虫, precisely deathwatch beetle). As of 2005, it was already the V850 era, and the V850 Family has been enjoying great success. As of 2018, it is called Renesas V850 Family and RH850 Family with V850/V850E1/V850E2 and V850E2/V850E3 CPU cores, respectively. Those CPU cores have extended ISA of original V810 CPU core; running with V850 compiler.
Emulator (CPU Simulator) Software
Because the V60/V70 had been used for many Japanese game arcades, their instruction set architecture has still survived as CPU simulator for this niche market. It is called MAME (Multiple Arcade Machine Emulator), which emulates multiple old game arcades for enthusiasts. It is a kind of an instruction set simulator, not for developers but for users.
Nowadays, it has been kept providing by the MAME development team. The latest open-source code, written in C++, is available from GitHub repository (<mamedev/mame></src/devices/cpu/v60/>). The operation codes in the file optable.hxx are exactly the same as those of V60.
NEC (November 1986). μPD70616 Programmer's Reference Manual (PRELIMINARY ed.). The Internet Archive, a 501(c)(3) non-profit.
EPUB, KINDLE, PDF, PDF w/text, FULL TEXT, etc, are available
Kani, Dr. Kenji (April 1987). Vシリーズマイクロコンピュータ 2 [V-Series Microcomputer 2] (in Japanese). Maruzen. ISBN 978-4621031575.
本書は日本電気(株)が、わが国ではじめて開発した32ビットマイクロプロセッサV60について解説したものである。[This book explains the V60, Japanese first developed 32-bit microprocessor by NEC.]
Mizuhashi, Yukiko; Teramoto, Msanoro (August 1989). "Real-time UNIX operating system: RX-UX 832". Microprocessing and Microprogramming. 27: 533–538. doi:10.1016/0165-6074(89)90105-1.
This paper describes requirements for real-time UNIX operating systems, design concept and the implementation of RX-UX 832 real-time UNIX operating system for v60/v70 microprocessor which are NEC's 32-bit microprocessors. RX-UX 832 is implemented adopting the building block structure, composed of three modules, real-time kernel, file-server and Unix supervisor. To guarantee a real-time responsibility, several enhancements were introduced such as, fixed priority task scheduling scheme, contiguous block file system and fault tolerant functions.
Thus, RX-UX 832 allows system designers to use standard Unix as its man-machine interface to build fault tolerant systems with sophisticated operability and provides high-quality software applications on the high performance microchips.
Komoto, Yasuhiko; Saito, Tatsuya; Mine, Kazumasa (1990-08-25). "Overview of 32-bit V-Series Microprocessor" (pdf). Journal of Information Processing. 13 (2): 110–122. ISSN 1882-6652. Retrieved 2018-01-08.
The advances in semiconductor manufacturing technology make it possible to integrate a floating-point unit and a memory management unit noto one microprocessor chip. They also permit the designers of a microprocessor to implement techniques used in the design of mainframe computers especially with regard to pipeline structures. The architecture of the V60 V70 and V80 was made possible by there advances. The V60 and V70 are NEC's first 32-bit microprocessors and include almost all the functions required by applied systems in a chip. The instruction set provides a high-level-language-oriented structure operating system sup-port functions and support functions for highly reliable systems. The V80 also employs the same architecture and achieves higher performance by means of cache memories and branch prediction mechanisms. The V80achieved a performance from two to four times higher than that of the V70.
Nakayama, T.; Harigai, H.; Kojima, S.; Kaneko, H.; Igarashi, H.; Toba, T.; Yamagami, Y.; Yano, Y. (Oct 1989). "A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions". IEEE Journal of Solid-State Circuits. 24 (5): 1324–1330. doi:10.1109/JSSC.1989.572608. ISSN 1558-173X.
An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on an 11.6*14.9-mm/sup 2/ die size.
Suzuki, Hiroaki; Sakai, Toshichika; Harigai, Hisao; Yano, Yoichi (1995-04-25). "A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor". IEICE TRANSACTIONS on Electronics. E78-C (4): 389–393. ISSN 0916-8516. Retrieved 2018-01-09.
A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 μm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm7.1 mm die.
- "Akatsuki: Dawn rises again at Venus". Retrieved 2018-01-07.
Hardenbergh, Hal W (1988). "RISCs CISCs and Fabs". Programmer's Journal. Avant-Garde Creations. 6 (2): 15.
So far we haven't mentioned two 32-bit CISC chips, the NEC V60/70 and the AT&T WE32 family. Unlike the NEC V20/25/30/50, the V60/70 is not based on the Intel architecture. NEC is targeting the V60/70 at embedded applications, ...
Yamahata, Hitoshi; Suzuki, Nariko; Koumoto, Yasuhiko; Shiiba, Tadaaki (1987-02-06). "マイクロプロセッサV60のアーキテクチャ" [Architecture of the microprocessor V60] (PDF). SIG Technical Reports; Microcomputer 43-2 (in Japanese). Information Processing Society of Japan. 1987 (8(1986-ARC-043)): 1–8. AN10096105.
This report will describe a single chip 32-bit CMOS VLSI microprocessor V60. It has been implemented by using a double metal-layer CMOS process technology with 1.5 um design rule to integrate 375,000 transistors. It integrates the virtual memory management unit for demand paging and the floating-point operations that conform to the IEEE-754 Floating-Point Standard. By using V20/V30 emulation mode, it can directly execute object programs of 16-bit CPU (V30). Instruction formats are suited to code-generation phase of compilers. 237 instructions are provided for high-level language and operating system. It can execute 3.5 MIPS (Million Instructions per Second) at 16-MHz operation with 16-bit data bus.
Sakamura, Ken (April 1988). "Recent Trends" (PDF). IEEE Micro. 8 (2): 10–11. ISSN 0272-1732. Retrieved 2018-01-08.
The V60/V70, NEC's proprietary CPU, is the first commercial-base, general-purpose, 32-bit microprocessor in Japan.
Rowen, C.; Przbylski, S.; Jouppi, N.; Gross, T.; Shott, J.; Hennessy, J. (1984). "A pipelined 32b NMOS microprocessor". 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXVII: 180–181. doi:10.1109/ISSCC.1984.1156607.
Sherburne, R. W.; Katevenis, M. G. H.; Patterson, D. A.; Sequin, C. H. (1984). "A 32-bit NMOS microprocessor with a large register file". IEEE Journal of Solid-State Circuits. 19 (5): 682–689. doi:10.1109/JSSC.1984.1052208. ISSN 0018-9200.
Riordan, T.; Grewal, G. P.; Hsu, S.; Kinsel, J.; Libby, J.; March, R.; Mills, M.; Ries, P.; Scofield, R. (1988). "The MIPS M2000 system". Proceedings 1988 IEEE International Conference on Computer Design: VLSI: 366–369. doi:10.1109/ICCD.1988.25724.
MIPS M2000 (R2000)
Namjoo, M.; Agrawal, A.; Jackson, D. C.; Quach, L. (1988). "CMOS gate array implementation of the SPARC architecture". Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference: 10–13. doi:10.1109/CMPCON.1988.4818.
SPARC, 1st Gen.
Kohn, L.; Fu, S. W. (1989). "A 1,000,000 transistor microprocessor". IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers: 54–55. doi:10.1109/ISSCC.1989.48231.
NEC (June 1997). 16-BIT V SERIES; INSTRUCTIONS (5 ed.). The Internet Archive, a 501(c)(3) non-profit.
EPUB, KINDLE, PDF, FULL TEXT, etc, are available.
Hennessy: Stanford University, John L; Patterson: University of California at Berkeley, David A. (2007). Computer Architecture: A Quantitative Approach (Fourth ed.). MORGAN KAUFMANN PUBLISHERA. ISBN 978-0-12-370490-0.
Open Access: EPUB, KINDLE, PDF, FULL TEXT, etc, are available.
Fu, B.; Saini, A.; Gelsinger, P. P. (1989). "Performance and microarchitecture of the i486 processor". Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors: 182–187. doi:10.1109/ICCD.1989.63352. ISBN 0-8186-1971-6.
The i486 microprocessor includes a carefully tuned, five-stage pipeline with an integrated 8-kB cache. A variety of techniques previously associated only with RISC (reduced-instruction-set computer) processors are used to execute the average instruction in 1.8 clocks. This represents a 2.5* reduction from its predecessor, the 386 microprocessor. The pipeline and clock count comparisons are described in detail. In addition, an onchip floating-point unit is included which yields a 4* clock count reduction from the 387 numeric coprocessor. The microarchitecture enhancements and optimizations used to achieve this goal, most of which are non-silicon-intensive, are discussed. All instructions of the 386 microprocessor and the 387 numeric coprocessor are implemented in a completely compatible fashion.
- Crawford, J.H. (February 1990). "The i486 CPU: executing instructions in one clock cycle". IEEE Micro. 10 (1): 27–36. doi:10.1109/40.46766. ISSN 0272-1732.
- "Despite its aging design, the x86 is still in charge". CNET.
Wade, James (1 October 1996). "A Community-Level Analysis of Sources and Rates of Technological Variation in the Microprocessor Market". Academy of Management Journal. 39 (5): 1218–1244. doi:10.2307/256997. ISSN 0001-4273.
7 The sponsors that did not use RISC technology were NEC, AT&T, and Followers of the TRON standard. All three of these microprocessors were specialized for users for whom performance was the highest priority. The Hitachi microprocessor followed the TRON standard, a high-performance CISC technology that, Japanese developers suggested, would be a viable alternative to RISC. The AT&T chip was portrayed as a chip suitable for building top-of-the-line, minicomputer-like computing systems. Similarly, NEC's V60 and V70 were patterned after one of NEC's 36-bit mainframe computers.
Kaneko, Hiroaki; Suzuki, Nariko; Wabuka, Hhiroaki; Maemura, Koji (April 1990). "Realizing the V80 and its system support functions". IEEE Micro. 10 (2): 56–69. doi:10.1109/40.52947. ISSN 0272-1732.
An overview is given of the architecture of an overall design considerations for the 11-unit, 32-b V80 microprocessor, which includes two 1-kB cache memories and a branch prediction mechanism that is a new feature for microprocessors. The V80's pipeline processing and system support functions for multiprocessor and high-reliability systems are discussed. Using V80 support functions, multiprocessor and high-reliability systems were realized without any performance drop. Cache memories and a branch prediction mechanism were used to improve pipeline processing. Various hardware facilities replaced the usual microprogram to ensure high performance.
Shimojima, Takehiko; Teramoto, Masanori (1987). "V60 real-time operating system". Microprocessing and Microprogramming. 21 (1–5): 197–204. doi:10.1016/0165-6074(87)90038-X. ISSN 0165-6074. Retrieved 2018-01-08.
This paper describes the requirements for 32-bit microprocessor real-time operating systems, design objectives and the implementation of the V60/V70 Real-Time Operating System (RTOS) and its programming supports.
Monden, Hiroshi; Teramoto, Takashi; Koga, Masanori (1986-03-14). "V60用アルタイムOSの検討 －32ビットI‑TRONに向けて－" [Feasibility study of real-time OS for the V60 - toward for the 32-bit I‑TRON -] (PDF). SIG (ARC) Technical Reports (in Japanese). Information Processing Society of Japan. 1986 (19(1985-ARC-061)): 1–8. AN10096105.
- "MAME:/src/emu/cpu/v60/v60.c". Mamedev.org. Archived from the original on 2014-02-22. Retrieved 2014-02-15.
Kimura, S.; Komoto, Y.; Yano, Y. (April 1988). "Implementation of the V60/V70 and its FRM function". IEEE Micro. 8 (2): 22–36. doi:10.1109/40.527.
A description is given of the V60/V70, the first commercially based, general-purpose 32-bit microprocessor in Japan. Its functions include on-chip floating-point operations, a high-level-language-oriented architecture, software debugging support, and support functions to promote a high level of system reliability. Because high reliability is so important, the V60/V70 contains functional redundancy monitoring (FRM) support functions. The discussion covers the overall design considerations, architecture, implementation, hazard detection and control, and FRM functions. The V60/V70 uses a TRON real-time operating system specification.
Yano, Y.; Koumoto, Y.; Sato, Y. (Spring 1988). "V60/V70 microprocessor and its systems support functions". Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference. pp. 36–42. doi:10.1109/CMPCON.1988.4824. ISBN 0-8186-0828-5.
Two advanced 32-bit microprocessors, the V60 and V70 ( mu PD70616 and mu PD70632, respectively), and their support functions for operating systems and high-reliability systems are described. Three operating system functions, namely, the virtual memory support functions, context-switch functions, and asynchronous trap functions are examined. A basic mechanism for high-reliability-system implementation, called FRM (functional redundancy monitoring), is discussed. FRM allows a system to be designed in which multiple V60s (or V70s) form a configuration in which one processor in the system acts as a master while the others act as monitors. An FRM board that uses three V60s in its redundant core is introduced.
Takahashi, Toshiya; Yano, Yoichi (1988-01-21). "V60/V70アーキテクチャ" [The Architecture of V60/V70 Microprocessors] (PDF). SIG Technical Reports (in Japanese). Information Processing Society of Japan. 1988 (4(1987-ARC-069)): 57–64. AN10096105.
This report describes the architecture of V60/V70 32-bit microprocessors. The architecture integrates various features into a single silicon die, such as a rich set of general purpose registers, high level language oriented instruction set, floating-point data handling which is suitable for scientific applications, and the FRM (Functionality Redundancy Monitoring) operation mode which supports highly-reliable systems configuration. These features will be introduced.
NEC (August 1986). "3-229". 1987 Microcomputer Data Book: Vol. 2 (PRELIMINARY ed.). The Internet Archive, a 501(c)(3) non-profit. pp. 266–268.
EPUB, KINDLE, PDF, FULL TEXT, etc, are available.
Yano, Yoichi (April 2012). "32ビット・マイコン「V60」開発物語" [Development story of the 32-bit microcomputer V60] (PDF) (in Japanese). Semiconductor History Museum of Japan. Retrieved 2018-01-08.
"ditto" (pdf). Bulletin "Encore" (in Japanese). Society of Semiconductor Industry Specialists. April 2012. pp. 17–20. Retrieved 2018-01-08.
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Richard Tan. "STS 145 Case Study Sega: The effect of corporate conflict on game design" (PDF).
"The Saturn originally ran on a NEC V60 chip at 16MHz. Compare this to the PlayStation CPU (MIPS R3000A 32bit RISC chip) which runs are 33.8MHz, almost double the speed. According to one Sega staff member, when Nakayama first received design specifications for the PlayStation, he was ‘the maddest I have ever seen him’, calling up the entire R&D division to his office to shout at them. An effort was made to compensate by adding another CPU for dual operation; however, this solution made the system so hard to develop for that, according to Yu Suzuki himself, “only 1 out of 100 programmers could use the Saturn to its full potential.”"
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- NEC LAUNCHES V80 ANSWER TO INTEL's 80486 - Computer Business Review, 1989-03-15 Balcklist:www.cbronline.com/news/nec_launches_v80_answer_to_intels_80486
- NEC MAY HAVE THE EDGE WITH ITS 930,000 TRANSISTOR V80 ANSWER TO INTEL'S 80486 - Computer Business Review, 1989-04-06 Balcklist:www.cbronline.com/news/nec_may_have_the_edge_with_its_930000_transistor_v80_answer_to_intels_80486
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- HISAO, SASAKI; AKIRA, SATO; TOSHIO, KARAKAMA (May 1993). "工業用コンピュータμPORT‐IIIと適用事例" [Applications of industrial computer .MU.PORT-III.]. 明電時報 [Meiden Jiho] (in Japanese) (230). ISSN 0386-1570.
Majithi, Kenneth (1987). "The New Generation of Microprocessors" (PDF). IEEE Micro. 7 (4): 4–5. doi:10.1109/MM.1987.304873. ISSN 0272-1732.
The Japanese have been equally aggressive in their new designs of high-performance microprocessors. NEC's V60 and V70 microprocessors use architectures that include not only the MMU but also an arithmetic floating-point unit on chip. Hitachi and Fujitsu have collaborated to produce a family of microprocessors adapted to the TRON operating system. These processors incorporate instruction pipelines as well as instruction and stack caches. However, unlike NEC, their FPU function is off chip.
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- Norihisa Suzuki (January 1992). Shared Memory Multiprocessing. MIT Press. p. 195. ISBN 978-0-262-19322-1.
- Office of Naval Research Asian Office, Scientific Information Bulletin, Vol 16, No. 3 July-September 1991, p. 3
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"MetaWare, Inc". crunchbase.
MetaWare, Inc. is a supplier of tools and technologies for software developers.
Santa Cruz, California, United States
MetaWare, Inc. is a privately held company operates as a supplier of tools and technologies for software developers.
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Cygnus Solutions (1999-02-25). "Patch to replace CYGNUS LOCAL with EGCS LOCAL in config.sub". gcc-patches (Mailing list).
I would like to submit the following patch. It renames all occurances of CYGNUS LOCAL to EGCS LOCAL, which seems slightly more accurate! :-)
Cygnus Solutions (1999-02-25). "Re: Patch to replace CYGNUS LOCAL with EGCS LOCAL in config.sub". gcc-patches (Mailing list).
Seems like a misguided exercise to me.
If the changes are truly Cygnus-specific, they should not be in Egcs. Otherwise, they should be merged into the config.sub master copy (whose maintainer, by the way, in Ben!).
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Harigai, Hisao; Kusuda, Masaori; Kojima, Shingo; Moriyama, Masatoshi; Ienaga, Takashi; Yano, Yoichi (1992-10-22). "低消費電力・低電圧動作の32ビットマイクロプロセッサV810" [A low power consumption and low voltage operation 32-bit RISC Microprocessor]. SIG Technical Reports, Information Processing Society of Japan. 1992 (82 (1992-ARC-096)): 41–48.
An advanced 32-bit RISC microprocessor for embedded control; V810 is introduced in this paper. The V810 has high performance and application specified functions. V810 dissipates less power than any other RISC chips. The V810 is the first 32-bit RISC microprocessor that operates at 2.2V.
The V810 chip is fabricated by using 0.8μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7mm2 die.
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Suzuki, K.; Arai, T.; Nadehara, K.; Kuroda, I. (1998). "V830R/AV: embedded multimedia superscalar RISC processor". IEEE Micro. 18 (2): 36–47. doi:10.1109/40.671401. ISSN 0272-1732.
The V830R/AV's real-time decoding of MPEG-2 video and audio data enables practical embedded-processor-based multimedia systems.
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Yano, Y; Iwasaki, J; Sato, Y; Iwata, T; Nakagawa, K; Ueda, M (Feb 1986). "A 32b CMOS VLSI microprocessor with on-chip virtual memory management". Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International. IEEE: 36–37. doi:10.1109/ISSCC.1986.1156924.
The execution unit (EXU) is a microprogrammed 32b data path processor which has thirty-two 32b general-purpose registers, sixteen 32b scratch-pad registers, a 64b barrel shifter, a 32b arithmetic logic unit (ALU); and a couple of control registers. Three data-buses that are running
"ditto". Research Gate.
Kaneko, H; Miki, Y; Koya, K; Araki, M (November 1986). "A 32-bit CMOS microprocessor with six-stage pipeline structure". Proceedings of 1986 ACM Fall joint computer conference. IEEE Computer Society Press: 1000–1007.
32-bit microprocessors are the key devices which carry high data processing capability, that was obtained by earlier general purpose computer systems and mini-computer systems, in much lower cost. Earlier 32-bit microprocessors were limited to adopt excellent architecture and design using appropriate hardware by number of devices could be fabricated on a chip. Complex functions such as Virtual Memory management and …
Kurosawa, A.; Yamada, K.; Kishimoto, A.; Mori, K.; Nishiguchi, N. (May 1987). "A Practical CAD System Application for Full Custom VLSI Microcomputer Chips". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 6 (3): 364–373. doi:10.1109/TCAD.1987.1270281. ISSN 1937-4151.
This paper presents a practical CAD system application for layout and verification, resulting in producible full-cutom VLSI microcomputer chips. The CAD system supports three design methodologies--symbolic layout mixed with mask level layout, compaction as an optimizer, and fully automated verification. For the area optimization, the symbolic layout and compactor subsystem supports a flexible description of orthogonal layout patterns with arbitrary dimensions in a loose placement manner. The layout patterns include path data, polygonal data, and symbolic cells. For power and delay optimization, the compactor compacts layout data, decreasing both resistance and capacitance for wires and ion-implanted layers. This feature is pioneering the new generation compactor. Emphasis should be put on the fact that it can compact layout data to a format 10-15 percent smaller than that accomplished manually. The verification subsystem can detect all kinds of errors, more than 30 items. A novel feature of the electrical rule check is that it investigates complementary logic errors for CMOS circuits. The synergy of those three design methodologies has brought about several significant advantages. One is manpower reduction by more than half, in the most complicated design process for unique random logic. The other is a 1600-transistors compaction output, smaller by 365 mils/sup 2/ than that manually compacted. The circuit implementation on a chip works at more than a 15 MHz clock rate. Another is the first silicon success. It has been accomplished in a full-custom VLSI microcomputer chip consisting of more than 100 000 transistors.
- Die photo of the V60; at Nikkei BP (in Japanese)
- Die photo of the V60; at Semiconductor History Museum of Japan (in Japanese)
- Die photo of the V60, mounted on PGA package (much clear, in Chinese)
- Die photo of the V60 with PGA packaging, removed ceramic cap (in Chinese)
- Photo of the V60 in PGA packaging w/ ceramic cap shield; glass shield
- Photo of the V60 in PGA packaging w/ metal cap shield; seam weld
- Blog: PS98-145-HMW kit: "PC-UX/V" w/ 15 disks & "V60 Sub board" for NEC PC-9801 slot (in Japanese)
- Article: V70 in PGA packaging and the H-IIA rocket (in English)
- Photo of NEC V60 CPU board of the Sega Virtua Racing (in English)
- Site: "System 16" - Sega System 32 Hardware (in English)
- Site: "System 16" - Sega Model 1 Hardware (in English)
- Site: "System 16" - Sega System Multi 32 Hardware (in English)
- Original documents for the V60 (μPD70616) & V70 (μPD70632) is available from here.
- Datasheets for the AFPP (μPD72691) is available from here.
- Renesas V850 Family web site
- Renesas RH850 Family web site