A relatively obscure design in the West, it was a radical departure from NEC's previous V-series CPUs—the NEC V20-V50 series—, which were based on the Intel x86 model, although it retained the ability to emulate them. According to NEC's documentation, the architectural change was made due to the increasing demand and diversity of programs, calling for a processor with both power (the 32-bit internal bus) and flexibility, having large numbers of general-purpose registers—a common feature of RISC architectures and a benefit to the emerging high-level languages. The V60 architecture retained however CISC features (which its manual describe as mainframe-based) like variable-length instructions, memory-to-memory operations including string manipulation, and fairly complex operand addressing schemes.
Although it had a 32-bit internal bus, the V60 had only a 16-bit external data bus and a 24-bit address bus. Its architecture was carried largely intact to the V70 (μPD70632) model, which had external 32-bit buses and was released in 1987. Launched in 1989, the V80 (μPD70832) was the culmination of the series having on-chip caches, a branch predictor, and less reliance on microcode for complex operations. The V60-V80 architecture did not enjoy much commercial success.
The operating systems developed for the V60-V80 series were generally oriented toward real-time operation. Having been used in some Japanese game arcade products, the V60 and V70 also survive in emulation software for this niche.
Work on the processor began in 1982 under the leadership of Yoichi Yano. About 250 engineers participated and the V60 (μPD70616) debuted in February 1986. It had a six-stage pipeline, built-in memory management unit and floating-point arithmetic. It was manufactured in 1.5 µm on a two-layer aluminum CMOS process using 375,000 transistors on a 13.9 × 13.8 mm die. It operated at 5 V and was initially packaged in a 68-pin PGA. The first version ran at 16 MHz at attained 3.5 MIPS. Its sample price at launch was set to ¥100,000 ($588.23). It entered full-scale production in August 1986.
Sega chose this processor for most of its arcade games in the 1990s; the Sega System 32 and Sega Model 1 architectures both used this as their main CPU. (The latter used the lower-cost μPD70615 variant, which doesn't implement V20/V30 emulation.) The V60 was also used as the main CPU in the SSV arcade architecture—so named because it was developed together by Seta, Sammy, and Visco. Sega originally considered using a 16-MHz V60 as the basis for its Sega Saturn console, but after receiving word of the PlayStation's processor (R3000A at 33.8 MHz) instead chose the dual-SH-2 design for the eventual production model.
In 1988, NEC released a kit called PS98-145-HMW for Unix enthusiasts. The kit contained a V60 processor board that could be plugged into select models of the PC-9800 computer series and a 15-floppy disk distribution of their PC-UX/V release 2.0. The suggested retail price for this kit was 450,000 Yen. NEC themselves included a V60 processor in their 1991 Bungo mini 5SX, 7SX, and 7SD word processor computers, where the V60 was used as fast outline font processor, while the main system processor was a 16 MHz NEC V33.
The V70 (μPD70632) improves on the V60 by making both the internal and external buses 32 bits wide. It was also manufactured in a 1.5 µm but two-metal layer process; its 14.35 × 14.24 mm die had 385,000 transistors and was packaged in a 132-pin ceramic PGA. Its MMU had support for demand paging. Its floating-point unit claimed IEEE-754 compliance. The 20 MHz version attained a peak performance of 6.6 MIPS and was priced at launch in August 1987 at ¥100,000 ($719.42). Initial production capacity was 20,000 units monthly. A later report describes it as fabricated in 1.2-micrometer CMOS and 12.23 × 12.32 mm die. The V70 had a bus cycle of only two internal cycles, whereas the V60 bus operated at 3 or 4 internal cycles.
A "space-spec" version of the V70 (running RX616) was included in the main computer module in the H-IIA rockets (the main launch vehicles used domestically in Japan) until their replacement in 2011 with a 64-bit HR5000 core.
The V80 (μPD70832) was launched in the spring of 1989. Incorporating on-chip caches and a branch predictor, it was declared NEC's 486 by Computer Business Review. The performance of the V80 was two to four times that of the V70, depending on the application. For example, unlike its V70 predecessor, the V80 had a 32-bit hardware multiplier reducing integer multiplication to 9 cycles compared to 23 cycles in the V70. (For more such differences, see next section.) The V80 was manufactured in a 0.8-micrometer CMOS process with a die area of 14.49 × 15.47 mm consisting of 980,000 transistors. It was packaged as a 280-pin PGA and operated at 25 or 33 MHz with a claimed peak performance of 12.5 and respectively 16.5 MIPS. The V80 had separate 1 KB on-die instruction and data caches and a 64-entry branch predictor; the performance gains attributed to the latter was about 5%. The launch prices if the V80 were cited as equivalent to $1200 for the 33 MHz and $960 for the 25 MHz version. Supposedly a 45 MHz version was scheduled for 1990, but this did not materialize.
The V60, V70, and V80 were listed in a 1990 NEC catalog in their PGA packaging. A NEC catalog from 1995 still listed the V60 and V70 (not only in their PGA version but also in a QFP packaging, and also included a low-cost variant of the V60 named μPD70615, which eliminated V20/V30 emulation), alongside their assorted chipset, but the V80 is not offered in this catalog. The 1999 edition of the same catalog no longer has any V60-V80 products.
The V60/V70/V80 mostly shared a common architecture. They had thirty-two 32-bit general-purpose registers, although the last three of these were commonly used as stack pointer, frame pointer and argument pointer. The V60 and V70 had a 119-instruction set, slightly extended to 123 instructions for the V80. The instructions have variable-length between one and 22 bytes, and they take two operands, both of which can be memory locations. After studying the V60's reference manual, Paul Vixie described it as "a very vax-ish arch, with a V20/V30 emulation mode (which, if you recall, means it can run Intel 8086/8088 software)".
V60-V80 had a built-in MMU that divide the 4 GB virtual address space into in four 1-GB sections, each section further divided in 1,024 1-MB areas, each area composed of 256 4-KB pages. On the V60/V70 four registers (ATBR0 to ATBR3) store section pointers on the processor, but the area tables entries (ATE) and page tables entries (PTE) are stored in RAM (off-chip). The V80 merged the ATE and ATBR registers, which are both on-chip with only the PTE entries stored in RAM, allowing for a faster execution of TLB misses by eliminating one memory read.
The TLBs on the V60/70 are 16-entry fully associative with replacement done by microcode/firmware. The V80 in contrast has a 64-entry 2-way set associative TLB with replacement done in hardware. TLB replacement took 58 cycles in the V70 and also disrupted the pipelined execution of other instructions. On the V80 a TLB replacement took only 6/11 cycles depending if the page was in the same area or not; pipeline disruption no longer occurred in V80 because of the separate TLB replacement hardware unit which operated in parallel to the rest of the processor.
All three processors used the same protection mechanism with 4 execution levels (set via a program status word), with ring 0 being the privileged level that could access a special set of privileged registers on the processors.
All three models supported a triple-mode redundancy configuration with three CPUs used in a byzantine fault tolerance scheme with bus freeze, instruction retry, and chip replacement signals. The V80 also added parity signals to its data and address buses.
String operations were implemented in microcode in the V60/V70, but aided by hardware Data Control Unit in the V80, running at full bus speed. This made string operations about five times faster in the V80.
All floating point operations are largely implemented in microcode across the family and thus and are fairly slow. On the V60/V70 the 32-bit floating point operations took 120/116/137 cycles for addition/multiplication/division, while the corresponding 64-bit floating point operations took 178/270/590 cycles. The V80 had some limited hardware assist for parts of the floating point operations, e.g. decomposition into sign, exponent and mantissa, thus its floating point unit was claimed up to 3 times as effective as the one of the V70, with 32-bit operations taking 36/44/74 cycles while 64-bit floating point operations taking 75/110/533 cycles on the V80 (again, for addition/multiplication/division).
To compensate for their fairly weak floating point performance, the V60/V70/V80 could be matched with a floating point coprocessor—the 80-bit μPD72691 released in 1989; This chip claimed 6.7 MFLOPS in the vector-matrix multiplication operating at 20 MHz. It was fabricated in 1.2-micrometer double-metal layer CMOS process and contained 433,000 transistors on a 11.6 × 14.9 mm die. This coprocessor connected to the V80 on a dedicated bus, but shared a common bus when used with the V60/V70, a scenario which diminished its peak performance.
NEC ported Unix System V to their V60 processor. (NEC's flavor of System V was called PC-UX/V; release 2.0 of this supported the V60.) NEC also developed a Unix variant for the V60/V70 with a focus on real-time operation called RX-UX832. An Ada 83 compiler was certified for this operating system for use on a machine called MV4000, which had a V70 processor and a VMEbus. A multiprocessor version of RX-UX832 was also developed and this was named MUSTARD. The MUSTARD-powered computer prototype used eight V70 processors.
The ITRON real-time operating system was also implemented by NEC for the V60/V70 and this implementation was given the name RX616. RX616 was a continuation of the work with RX116, a similar operating system for the 16-bit microprocessors series V20-V50.
The V60 could also run CP/M and DOS programs (from the V20-V50 series) using emulation. According to a 1991 article in InfoWorld, Digital Research was working on a version of Concurrent DOS for the V60 at some point, but this was never released as the V60/V70 processors were not imported in the US for use in PC clones. In 1987 Digital Research also had announced that they were planning on porting FlexOS to the V60 and V70.
- "Programmer's Journal". 6 (2). Avant-Garde Creations. 1988: 15.
So far we haven't mentioned two 32-bit CISC chips, the NEC V60/70 and the AT&T WE32 family. Unlike the NEC V20/25/30/50, the V60/70 is not based on the Intel architecture.
- Ken Sakamura, "Recent Trends", IEEE Micro, April 1988, pp. 10-11
- NEC V60 Programmer's Reference Manual
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- Dataquest, "Japanese Semiconductor Industry Service", 1st Quarter 1986, p. 18 (pdf p. 44 in this multi-volume archive)
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- Richard Tan. "STS 145 Case Study Sega: The effect of corporate conflict on game design" (PDF).
The Saturn originally ran on a NEC V60 chip at 16MHz. Compare this to the PlayStation CPU (R3000A 32bit RISC chip) which runs are 33.8MHz, almost double the speed. According to one Sega staff member, when Nakayama first received design specifications for the PlayStation, he was ‘the maddest I have ever seen him’, calling up the entire R&D division to his office to shout at them. An effort was made to compensate by adding another CPU for dual operation; however, this solution made the system so hard to develop for that, according to Yu Suzuki himself, “only 1 out of 100 programmers could use the Saturn to its full potential.”
- 型 名 ：PS98-145-HMW 品 名 ：PC-UX/V(Rel2.0)(V60), NEC product sheet
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- NEC MAY HAVE THE EDGE WITH ITS 930,000 TRANSISTOR V80 ANSWER TO INTEL'S 80486 by CBR Staff Writer| 06 April 1989 
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