The NVAX is a microprocessor developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). The NVAX was a high-end single-chip VAX microprocessor. A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX is clocked at frequencies of 83.3 MHz (12 ns), 71 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns).
The NVAX and NVAX+ was used in late-model VAX systems released in 1991 such as the MicroVAX 3100, VAXstation 4000, VAX 4000, VAX 6000, VAX 7000/10000 and VAXft. Although Digital updated the design throughout the early 1990s, the processors and the VAX platform itself was ultimately superseded by the introduction of the DECchip 21064, an implementation of the Alpha (then Alpha AXP) architecture, and the resulting systems in November 1992.
NVAX contained 1.3 million transistors on a die measuring 16.2 by 14.6 mm in size (236.52 mm²). The die was fabricated in Digital's fourth-generation CMOS process, CMOS-4, a 0.75 µm process with three layers of aluminium interconnect. The NVAX is packaged in a 339-pin pin grid array while the NVAX+ is packaged in a 431-pin pin grid array that is compatible with the Alpha AXP-based DECchip 21064 microprocessor.
In 1994, a variant of the NVAX+, the NVAX++ (also known as NV5) was introduced in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in Digital's fifth-generation CMOS process, CMOS-5, a 0.50 µm process. In 1996, a 170.9 MHz NV5 was introduced, used in the VAX 7000/10000 Model 8x0.
The NVAX is partitioned into the five semi-autonomous units, the I-box, E-box, F-box, M-box and C-box. The NVAX is macropipelined. Multiple VAX macroinstructions are processed in parallel by autonomous units, which have their own micropipelines.
The I-box fetches and decodes VAX instructions. It also contains the 2 KB direct-mapped virtual instruction cache (VIC) and the 512-entry by 4-bit branch history table. The I-box aimed to fetch eight bytes of instruction data from the VIC during every cycle.
The F-box executes floating-point instructions as well as 32-bit integer multiply instructions. It has a four-stage floating-point and integer multiply pipeline and a non-pipelined floating-point divider.
- Uhler, Michael G. et al. "The NVAX and NVAX+ High-performance VAX Microprocessors". Digital Technical Journal, Volume 4, Number 3, Summer 1992. pp. 11–23.
- Digital Technical Journal: special issue on NVAX-microprocessor VAX systems. (Digital Equipment Corporation)4 (3). Summer 1992. ISSN 0898-901X.
- Anderson, W. (1992). "Logical verification of the NVAX CPU chip design". Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors. pp. 306–309. ISBN 0-8186-3110-4.
- Badeau, R.W. et al. (1992). "A 100-MHz macropipelined VAX microprocessor". IEEE Journal of Solid-State Circuits, Volume 27, Issue 11. pp. 1585–1598. ISSN 0018-9200.
- Fox, Thomas F. (1994). "The design of high-performance microprocessors at Digital". Proceedings of the 31st Annual ACM-IEEE Design Automation Conference. pp. 586–591.