National Semiconductor SC/MP

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PMOS SC/MP die (ISP-8A/500)

National Semiconductor's INS8060, or SC/MP (pronounced scamp) for Simple Cost-effective Micro Processor, is an early 8-bit microprocessor which became available in April 1976. A unique feature of the SC/MP is a daisy-chained control pin that allowed up to three SC/MP's share a single main memory to produce a multiprocessor system.

To lower cost, the system used a bit-serial arithmetic logic unit (ALU) and was thus significantly slower than contemporary designs like the Intel 8080 or MOS 6502 which had parallel ALUs. Another oddity was that the program counter could only access the lower 12-bits of the 16-bit address, and the upper 4-bits had to be set using special instructions. The result was that instructions accessed main memory as sixteen 4 kB "pages" and reaching memory outside those pages required multiple instructions.[a]

The combination of slow speed and paged memory limited its attractiveness, especially in the markets that might need a multiprocessing system. It saw very little use in the market.

NS SC/MP registers
15 . . . 07 . . . 00 (bit position)
Pointer registers
P0 (PC) Pointer 0/Program Counter
P1 Pointer 1
P2 Pointer 2
P3 Pointer 3
  A Accumulator
  E Extension
Program Status Register
7 6 5 4 3 2 1 0 (bit position)
CY OV SB SA IE F2 F1 F0 Status


Basic features[edit]

Like most 8-bit microprocessors of the era, the SC/MP is based around a 16-bit address and an 8-bit data bus. To lower pin count, the external address bus contains only 12 pins, sharing 4 pins from the data bus to create a complete 16-bit address. Internally, the program counter is twelve bits wide, and there are separate instructions to set the upper four bits. This provides a memory map of sixteen four-kilobyte pages, and program code could not refer to code or data outside its own page. Internally it provided five registers plus the program counter. Subroutine and Interrupt handling were implemented by Pointer Register 3 (P3) although this could also be used as a general purpose 16 bit Index register.

Bus control[edit]

A unique feature of the SC/MP was a shared daisy-chained control line that allowed multiple SC/MP, or more commonly a single SC/MP and related direct memory access controllers, to share access to a single main memory. When any one of the chips on the bus desired access to memory, it would set the ENOUT pin high, thereby signalling the other chip's ENIN pins that they had to release the bus. With other processors, this would normally require external logic implemented by the board designers to pause the CPU to the same end, often with some complexity due to the internal instruction timing that was not visible to the external circuits. In the SC/MP this was all included internally so a single line on the circuit board was all that was needed to implement this feature.

The original idea was to ease the creation of microcontroller-like applications containing an SC/MP, one or more DMA controllers, and a single shared memory. Designed specifically to be as low-cost as possible in terms of an overall system, the desire to lower the cost of the SC/MP itself also led to decisions about the bit-serial ALU and the inclusion of serial input/output lines to eliminate the need for a separate UART (this feature was removed in the later SC/MP III).

SC/MP unusual features[edit]

SC/MP increments the program counter before fetching the instruction, so that on reset it actually starts executing instructions from location 0001. This also needs to be taken into account for calculating displacements, since the offset will be added to the program counter which will be still pointing to the location of the displacement and not the next instruction.


NMOS SC/MP-2 die (ISP-8A/600)

ISP-8A/500 SC/MP-1 Clocked at 1 MHz, first implementation (P Channel MOS technology)

INS 8060 ISP-8A/600 SC/MP-2 Clocked at 4 MHz (internally 2 MHz) first N Channel MOS version (single +5V supply)

INS 807x SC/MP-3 Clocked at 4 MHz (internally 2 MHz) included variations with up to 4 KB ROM (optional onboard BASIC (NIBL))


The SC/MP was also used as the basis of a single board microcontroller produced by Science of Cambridge (later Sinclair Research Ltd) called the MK14. Montgomery Elevator Co of Moline IL (later purchased by KONE, Inc) used the SC/MP as the basis for its first micro processor based elevator controller released in 1975. There are still many of these units running in buildings across the U.S.A.


  1. ^ This segmented memory approach was more famous in the Intel 8088.