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Overview of electronic signal termination
In lower frequency (slow edge rate) applications, interconnection lines can be modelled as "lumped" circuits. In this case there is no need to consider the concept of "termination". Under the low frequency condition, every point in an interconnect wire can be assumed to have the same voltage as every other point for any instance in time.
However, if the propagation delay in a wire, PCB trace, cable, or connector is greater than 1/6 of the rise time of the digital signal, the "lumped" circuit model is no longer valid and the interconnect has to be analyzed as a transmission line. In a transmission line, the signal interconnect path is modeled as a circuit containing distributed inductance, capacitance and resistance throughout its length.
In order for a transmission line to minimize distortion of the signal, the impedance of every location on the transmission line should be uniform throughout its length. If there is any place in the line where the impedance is not uniform for some reason (open circuit, impedance discontinuity, different material) the signal gets modified by reflection at the impedance change point which results in distortion, ringing and so forth.
When the signal path has impedance discontinuity, in other words an impedance mismatch, then a termination impedance with the equivalent amount of impedance is placed at the point of line discontinuity. This is described as "termination". For example resistors can be placed on computer mother boards to terminate high speed busses. There are several ways of termination depending on how the resistors are connected to the transmission line. Parallel termination and series termination are examples of termination methodologies.
Instead of having the necessary resistive termination located on the motherboard, the termination is located inside the semiconductor chips–technique called On-Die Termination (abbreviated to ODT).
Why is on-die termination needed?
Although the termination resistors on the motherboard reduce some reflections on the signal lines, they are unable to prevent reflections resulting from the stub lines that connect to the components on the module card (e.g. DRAM Module). A signal propagating from the controller to the components encounters an impedance discontinuity at the stub leading to the components on the module. The signal that propagates along the stub to the component (e.g. DRAM component) will be reflected back onto the signal line, thereby introducing unwanted noise into the signal. In addition, on-die termination can reduce the number of resistor elements and complex wiring on the mother board. Accordingly, the system design can be simpler and cost effective.
Example of ODT: DRAM
On-die termination is implemented with several combinations of resistors on the DRAM silicon along with other circuit trees. DRAM circuit designers can use a combination of transistors which have different values of turn-on resistance. In the case of DDR2, there are three kinds of internal resistors 150ohm, 75ohm and 50ohm. The resistors can be combined to create a proper equivalent impedance value to the outside of the chip, whereby the signal line (transmission line) of the motherboard is being controlled by the on-die termination operation signal. Where an on-die termination value control circuit exists the DRAM controller manages the on-die termination resistance through a programmable configuration register which resides in the DRAM. The internal on-die termination values in DDR3 are 120ohm, 60ohm, 40ohm and so forth.