|Max. CPU clock rate||2.5 GHz to 5 GHz|
|Min. feature size||22 nm|
|Instruction set||Power Architecture (Power ISA v.2.07)|
|Cores||4, 6, 8, 10 or 12|
|L1 cache||64+32 KB per core|
|L2 cache||512 KB per core|
|L3 cache||8 MB per chiplet|
|L4 cache||16 MB per Centaur|
|Made by Freescale|
|Made by IBM|
|Cancelled in gray, historic in italic|
POWER8 is a family of superscalar symmetric multiprocessors based on the Power Architecture, announced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for such availability of IBM's highest-end processors.
Systems based on POWER8 became available from IBM in June 2014. Systems and POWER8 processor designs made by other OpenPOWER members was available in early 2015, but Tyan seems to be ready to ship earlier than that, in October 2014.
More details and documentation on POWER8 can be found on the IBM Portal for OpenPOWER.
POWER8 is designed to be a massively multithreaded chip, with each of its cores capable of handling eight hardware threads simultaneously, for a total of 96 threads executed simultaneously on a 12-core chip. The processor makes use of very large amounts of on- and off-chip eDRAM caches, and on-chip memory controllers enable very high bandwidth to memory and system I/O. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the POWER7.
POWER8 comes in 4-, 6-, 8-, 10- and 12-core variants; each version is fabricated in a 22 nm silicon on insulator (SOI) process using 15 metal layers. The 12-core version consists of 4.2 billion transistors and is 650 mm2 large while the 6-core version is only 362 mm2 large.
Where previous POWER processors use the GX++ bus for external communication, POWER8 removes this from the design and replaces it with the CAPI port (Coherent Accelerator Processor Interface) that is layered on top of PCI Express 3.0. The CAPI port is used to connect auxiliary specialized processors such as GPUs, ASICs and FPGAs. Units attached to the CAPI bus can use the same memory address space as the CPU, thereby reducing the computing path length. At the 2013 ACM/IEEE Supercomputing Conference, IBM and Nvidia announced an engineering partnership to closely couple POWER8 with Nvidia GPUs in future HPC systems, with the first of them announced as the Power Systems S824L.
POWER8 also contains a so-called on-chip controller (OCC), which is a power and thermal management microcontroller based on a PowerPC 405 processor. It has two general-purpose offload engines (GPEs) and 512 KB of embedded static RAM (SRAM), together with the possibility to access the main memory directly, while running an open-source firmware. OCC manages POWER8's operating frequency, voltage, memory bandwidth, and thermal control for both the processor and memory; it can regulate voltages through 1,764 integrated voltage regulators (IVRs) on the fly. Also, the OCC can be programmed to overclock the POWER8 processor, or to lower its power consumption by reducing the operating frequency (which is similar to the configurable TDP found in some of the Intel and AMD processors).
The memory controllers on the POWER8 chips are specified to use either DDR3 or DDR4 memory but are designed to be future-proof by being generic memory controllers paired to an external component called Centaur that acts as a memory buffer, L4 cache chip and the actual memory controllers. The current Centaur chip is using DDR3 memory, but a future version can use DDR4 or some other memory technology without the need to modify the design of the POWER8 chip itself.
Every Centaur is connected to the POWER8 by means of three high-speed links (2:1 Read:Write), each running at 9.6 GB/s, for a total bandwidth of 28.8 GB/s, with a 40 ns latency. Centaur contains 16 MB of eDRAM which can be used as L4 cache by the processor. Each POWER8 can be linked to up to eight Centaur chips allowing for up to 1 TB of memory per socket, with an aggregated 128 MB L4 cache and 230 GB/s sustained memory bandwidth in and out of the processor, with a total of 32 DRAM ports and 410 GB/s peak memory bandwidth at the DRAM. Centaur chips are mounted onto DRAM DIMM modules.
The Centaur chips are fabricated with a process similar to that of the POWER8.
The POWER8 core has 64 KB L1 data cache contained in the load-store unit and 32 KB L1 instruction cache contained in the instruction fetch unit, along with a tightly integrated 512 KB L2 cache. In a single cycle each core can fetch up to eight instructions, decode and dispatch up to eight instructions, issue and execute up to ten instructions and commit up to eight instructions. Each Power8 core consist of primarily the following six execution units:
- Instruction Fetch Unit (IFU)
- Instruction Sequencing Unit (ISU)
- Load-store unit
- Fixed-point unit (FXU)
- Vector and Scalar Unit (VSU)
- Decimal floating point unit (DFU)
Each core has sixteen execution pipelines:
- Two fixed-point pipelines
- Two load-store pipelines
- Two load pipelines
- Four double-precision floating-point pipelines, which can also act as eight single-precision pipelines
- Two fully symmetric vector pipelines with support for VMX and VSX AltiVec instructions.
- One cryptographic pipeline (AES, Galois Counter Mode, SHA-2)
- One branch execution pipeline
- One condition register logical pipeline
- One decimal floating-point pipeline
It has a larger issue queue with 4×16 entries, improved branch predictors and can handle twice as many cache misses. Each core is eight-way hardware multithreaded and can be dynamically and automatically partitioned to have either one, two, four or all eight threads active. POWER8 also added support for hardware transactional memory. IBM estimates that each core is 1.6 times as fast as the POWER7 in single-threaded operations.
A POWER8 processor is a 12-chiplet design with variants consisting of either 4, 6, 8, 10 or 12 chiplets, in which one chiplet consists of one core, 512 KB of SRAM L2 cache on a 64-byte wide bus (which is twice as wide as on its predecessor), and 8 MB of L3 eDRAM cache per chiplet shareable among all chiplets. Thus, a six-chiplet processor would have 48 MB of L3 eDRAM cache, while a 12-chiplet processor would have a total of 96 MB of L3 eDRAM cache. The chip can also utilize an up to 128 MB of off-chip eDRAM L4 cache using Centaur companion chips. The on-chip memory controllers can handle 1 TB of RAM and 230 GB/s sustained memory bandwidth. The on-board PCI Express controllers can handle 48 GB/s of I/O to other parts of the system. The cores are designed to operate at clock rates between 2.5 and 5 GHz.
The six-core version is mounted in pairs on dual-chip modules (DCM) in IBM's Scale Out servers. In most configurations not all cores are active, resulting in a variety of configurations where the actual core count differs. The 12-core version has not been released in any system as of May 2014[update].
POWER8 with NVLink
This is a revised version of the original 12-core POWER8 from IBM, and used to be called POWER8+. The main new feature is that it has support for Nvidia's bus technology NVLink, connecting up to four NVLink devices directly to the chip. IBM removed the A Bus and PCI interfaces for SMP connections to other POWER8 sockets and replaced them with NVLink interfaces. Connection to a second CPU socket are now provided via the X Bus. Besides that and a slight size increase to 659 mm2, the differences seem minimal compared to previous POWER8 processors.
On 19 January 2014, the Suzhou PowerCore Technology Company announced that they will join the OpenPOWER Foundation and license the POWER8 core to design custom-made processors for use in big data and cloud computing applications.
- IBM Murano – a 12-core processor with two six-core chips. Scale-out processor is available in configurations with disabled cores.
- IBM Turismo – a single-chip 12-core processor. Scale-up processor is commercially available for licensing and purchase in configurations with disabled cores.
- PowerCore CP1 – a POWER8 variant with revised security features due to export restrictions between United States and China that will be manufactured in Global Foundries (formerly IBM's plant) factory in East Fishkill, New York. To be released in 2015.
- Scale Out servers, supporting one or two sockets each carrying a dual-chip module with two six-core POWER8 processors. They come in either 2U or 4U form factors, and one tower configuration. The "L" versions run only Linux, while the others run AIX, IBM i and Linux. The "LC" versions are built by OpenPOWER partners.
- Power Systems S812L – 1× POWER8 DCM (4, 6 or 8 cores), 2U
- Power Systems S814 – 1× POWER8 DCM (6 or 8 cores), 4U or tower
- Power Systems S822 and S822L – 1× or 2× POWER8 DCM (6, 10, 12 or 20 cores), 2U
- Power Systems S824 and S824L – 1× or 2× POWER8 DCM (6, 8, 12, 16 or 24 cores), 4U
- Power Systems S821LC "Stratton" – 2× POWER8 SCM (8 or 10 cores), 1U. Up to 512 GB DDR4 RAM buffered by four Centaur L4 chips. Manufactured by Supermicro.
- Power Systems S822LC for Big Data "Briggs" – 2× POWER8 SCM (8 or 10 cores), 2U. Up to 512 GB DDR4 RAM buffered by four Centaur L4 chips. Manufactured by Supermicro.
- Enterprise servers, supporting nodes with four sockets, each carrying 8-, 10- or 12-core modules, for a maximum of 16 sockets, 128 cores and 16 TB of RAM. These machines can run AIX, IBM i, or Linux.
- Power Systems E850 – 2×, 3× or 4× POWER8 DCM (8, 10 or 12 cores), 4U
- Power Systems E870 – 1× or 2× 5U nodes, each with four sockets with 8- or 10-core POWER8 single-chip modules, for up to a total of 80 cores
- Power Systems E880 – 1x, 2x, 3x or 4x 5U nodes, each with four sockets with 8- or 12-core POWER8 single-chip modules for up to a total of 192 cores
- High performance computing:
- Power Systems S812LC – 1× POWER8 SCM (8 or 10 cores), 2U. Manufactured by Tyan.
- Power Systems S822LC "Firestone" – 2× POWER8 SCM (8 or 10 cores), 2U. Two Nvidia Tesla K80 GPUs and up to 1 TB commodity DDR3 RAM. Manufactured by Wistron.
- Power Systems S822LC for HPC "Minsky" – 2× POWER8+ SCM (8 or 10 cores), 2U. Up to four NVLinked Nvidia Tesla P100 GPUs and up to 1 TB commodity DDR4 RAM. Manufactured by Wistron.
- An ATX motherboard with one single-chip POWER8 socket called the SP010GM2NR.
- Palmetto GN70-BP010, OpenPower reference system. 2U server, with one four-core POWER8 SCM, four RAM sockets, based on a Tyan's motherboard.
- Habanero TN-71-BP012. 2U, with one 8 core POWER8 SCM, 32 RAM sockets
- GT75-BP012. 1U, with a single 8- or 10-core POWER8 SCM and 32 sockets for RAM modules
- Google has shown a motherboard with two sockets, intended for internal use only.
- StackVelocity has designed a high-performance reference platform, Saba.
- Inspur has made a deal with IBM to develop server hardware based on POWER8 and related technologies.
- 4U server, two POWER8 sockets.
- RM4950 – 4U, 4-core POWER8 SCM with four Nvidia Tesla K40 accelerators. Based on Tyan's motherboard.
- Zoom Netcom
- RedPOWER C210 and C220 – 2U and 4U servers with two POWER8 sockets and 64 sockets for RAM modules.
- RedPOWER C310 and C320 – 2U and 4U servers with two CP1 sockets.
- OP-1X – 1U, single socket, 32 RAM slots.
- Barreleye – 1U, 2 socket, 32 RAM slots. Based on the Open Compute Project platform for use in their OnMetal service.
- You won't find this in your phone: A 4GHz 12-core Power8 for badass boxes
- POWER8 Processor User’s Manual for the Single-Chip Module
- IBM POWER8 - Announce / Availability Plans
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- Leonidas Barbosa (September 21, 2015). "POWER8 in-core cryptography". IBM.
- "Performance Optimization and Tuning Techniques for IBM Processors, including IBM POWER8" (PDF). IBM. July 2014. Retrieved February 8, 2015.
- Wei Li (November 18, 2014). "IBM XL compiler hardware transactional memory built-in functions for IBM AIX on IBM POWER8 processor-based systems". IBM. Retrieved February 8, 2015.
- Harold W. Cain, Maged M. Michael, Brad Frey, Cathy May, Derek Williams, and Hung Le. "Robust Architectural Support for Transactional Memory in the Power Architecture." In ISCA '13 Proceedings of the 40th Annual International Symposium on Computer Architecture, pp. 225-236, ACM, 2013. doi:10.1145/2485922.2485942
- Power8 Iron To Take On Four-Socket Xeons, nextplatform.com, 2015-05-11
- OpenPOWER and the Roadmap Ahead – Brad McCredie
- IBM Debuts Power8 Chip with NVLink and 3 New Systems
- Whitepaper - NVIDIA Tesla P100 - The Most Advanced Datacenter Accelerator Ever Built Featuring Pascal GP100, the World’s Fastest GPU
- IBM Power Systems S822LC for High Performance Computing Technical Overview and Introduction
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- OpenPower Collective Opens For System Business / nextplatform.com, 2015-03
- Foundation Unveils Slew of OpenPOWER Firsts
- IBM Power Systems E870 and E880 Technical Overview and Introduction
- IBM Announces POWER8 with OpenPOWER Partners
- "IBM News room - 2014-04-23 IBM Tackles Big Data Challenges with Open Server Innovation Model - United States". Retrieved 17 December 2014.
- Scale-out Hardware with POWER8 Technology
- Refreshed IBM Power Linux Systems Add NVLink
- IBM Power Systems E870 and E880 Technical Overview and Introduction
- IBM Back In HPC With Power Systems LC Clusters / nextplatform.com, 2015-10
- IBM’s First OpenPOWER Server Targets HPC Workloads
- OpenPOWER Foundation Technology Leaders Unveil Hardware Solutions To Deliver New Server Alternatives
- IBM's new Power8 server packs in Nvidia's speedy NVLink interconnect
- Tyan OpenPOWER System
- TYAN Debuts New POWER8-Based 1U Sever at OpenPOWER Summit 2016
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- 14 Views of the Open Power Summit
- Cirrascale RM4950 / Multi-Device POWER8® Development Platform
- RedPOWER Products page
- OpenPower Group Puts Initial Hardware Products on Display
- OpenPOWER: Opening The Stack, All The Way Down
- Rackspace Building OpenPOWER-Based Open Compute Server
- Life at the Intersection: OpenPOWER, Open Compute, and the Future of Cloud Software & Infrastructure
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