In computer data storage, partial-response maximum-likelihood (PRML) is a method for recovering the digital data from the weak analog read-back signal picked up by the head of a magnetic disk drive or tape drive. PRML was introduced to recover data more reliably or at a greater areal-density than earlier simpler schemes such as peak-detection. These advances are important because most of the digital data in the world is stored using magnetic storage on hard disk or tape drives.
Ampex introduced PRML in a tape drive in 1984. IBM introduced PRML in a disk drive in 1990 and also coined the acronym PRML. Many advances have taken place since the initial introduction. Recent read/write channels operate at much higher data-rates, are fully adaptive, and, in particular, include the ability to handle nonlinear signal distortion and non-stationary, colored, data-dependent noise (PDNP or NPML).
Partial response refers to the fact that part of the response to an individual bit may occur at one sample instant while other parts fall in other sample instants. Maximum-likelihood refers to the detector finding the bit-pattern most likely to have been responsible for the read-back waveform.
Partial-response was first proposed by Adam Lender in 1963. The method was generalized by Kretzmer in 1966. Kretzmer also classified the several different possible responses, for example, PR1 is duobinary and PR4 is the response used in the classical PRML. In 1970, Kobayashi and Tang recognized the value of PR4 for the magnetic recording channel.
By 1971, Hisashi Kobayashi at IBM had recognized that the Viterbi algorithm could be applied to analog channels with inter-symbol interference and particularly to the use of PR4 in the context of Magnetic Recording (later called PRML). (The wide range of applications of the Viterbi algorithm is well described in a review paper by Dave Forney.) A simplified algorithm, based upon a difference metric, was used in the early implementations. This is due to Ferguson at Bell Labs.
Implementation in products
The first two implementations were in Tape (Ampex - 1984) and then in hard disk drives (IBM - 1990). Both are significant milestones with the Ampex implementation focused on very high data-rate for a digital instrumentation recorder and IBM focused on a high level of integration and low power consumption for a mass-market HDD. In both cases, the initial equalization to PR4 response was done with analog circuitry but the Viterbi algorithm was performed with digital logic. In the tape application, PRML superseded 'flat equalization'. In the HDD application, PRML superseded RLL codes with 'peak detection'.
The first implementation of PRML was shipped in 1984 in the Ampex Digital Cassette Recording System (DCRS). The chief engineer on DCRS was Charles Coleman. The machine evolved from a 6-head, transverse-scan, digital video tape recorder. DCRS was a cassette-based, digital, instrumentation recorder capable of extended play times at very high data-rate. It became Ampex' most successful digital product.
The heads and the read/write channel ran at the (then) remarkably high data-rate of 117 Mbits/s. The PRML electronics were implemented with four 4-bit, Plessey analog-to-digital converters (A/D) and 100k ECL logic. The PRML channel outperformed a competing implementation based on "Null-Zone Detection". A prototype PRML channel was implemented earlier at 20 Mbit/s on a prototype 8-inch HDD, but Ampex exited the HDD business in 1985. These implementations and their mode of operation are best described in a paper by Wood and Petersen. Petersen was granted a patent on the PRML channel but it was never leveraged by Ampex.
Hard disk drives
In 1990, IBM shipped the first PRML channel in an HDD in the IBM 0681 It was full-height 5¼-inch form-factor with up to 12 of 130 mm disks and had a maximum capacity of 857 MB.
The PRML channel for the IBM 0681 was developed in IBM Rochester lab. in Minnesota with support from the IBM Zurich Research lab. in Switzerland. A parallel R&D effort at IBM San Jose did not lead directly to a product. A competing technology at the time was 17ML an example of Finite-Depth Tree-Search (FDTS).
The IBM 0681 read/write channel ran at a data-rate of 24 Mbits/s but was more highly integrated with the entire channel contained in a single 68-pin PLCC integrated circuit operating off a 5 volt supply. As well as the fixed analog equalizer, the channel boasted a simple adaptive digital cosine equalizer after the A/D to compensate for changes in radius and/or changes in the magnetic components.
The presence of nonlinear transition-shift (NLTS) distortion on NRZ recording at high density and/or high data-rate was recognized in 1979. The magnitude and sources of NLTS can be identified using the 'extracted dipulse' technique.
Ampex was the first to recognize the impact of NLTS on PR4. and was first to implement Write precompensation for PRML NRZ recording. 'Precomp.' largely cancels the effect of NLTS. Precompensation is viewed as a necessity for a PRML system and is important enough to appear in the BIOS HDD setup although it is now handled automatically by the HDD.
PR4 is characterized by an equalization target (+1, 0, -1) in bit-response sample values or (1-D)(1+D) in polynomial notation (here, D is the delay operator referring to a one sample delay). The target (+1, +1, -1, -1) or (1-D)(1+D)^2 is called Extended PRML (or EPRML). The entire family, (1-D)(1+D)^n, was investigated by Thapar and Patel. The targets with larger n value tend to be more suited to channels with poor high-frequency response. This series of targets all have integer sample values and form an open eye-pattern (e.g. PR4 forms a ternary eye). In general, however, the target can just as readily have non-integer values. The classical approach to maximum-likelihood detection on a channel with intersymbol interference (ISI) is to equalize to a minimum-phase, whitened, matched-filter target. The complexity of the subsequent Viterbi detector increases exponentially with the target length - the number of states doubling for each 1-sample increase in target length.
Given the rapid increase in complexity with longer targets, a post-processor architecture was proposed, firstly for EPRML. With this approach a relatively simple detector (e.g. PRML) is followed by a post-processor which examines the residual waveform error and looks for the occurrence of likely bit pattern errors. This approach was found to be valuable when it was extended to systems employing a simple parity check
PRML with nonlinearities and signal-dependent noise
As data detectors became more sophisticated, it was found important to deal with any residual signal nonlinearities as well as pattern-dependent noise (noise tends to be largest when there is a magnetic transition between bits) including changes in noise-spectrum with data-pattern. To this end, the Viterbi detector was modified such that it recognized the expected signal-level and expected noise variance associated with each bit-pattern. As a final step, the detectors were modified to include a 'noise predictor filter' thus allowing each pattern to have a different noise-spectrum. Such detectors are referred to as Pattern-Dependent Noise-Prediction (PDNP) detectors or noise-predictive maximum-likelihood detectors (NPML). Such techniques have been more recently applied to digital tape recorders.
Although the PRML acronym is still occasionally used, advanced detectors are more complex PRML operate at higher data-rates. The analog front-end typically includes AGC, correction for the nonlinear read-element response, and a low-pass filter with control over the high-frequency boost or cut. Equalization is done after the ADC with a digital FIR filter. (TDMR uses a 2-input, 1-output equalizer.) The detector uses the PDNP/NPML approach but the hard-decision Viterbi algorithm is replaced with a detector providing soft-outputs (additional information about the reliability of each bit). Such detectors using a soft Viterbi algorithm or BCJR algorithm are essential in iteratively decoding the low-density parity-check code used in modern HDDs. A single integrated circuit contains the entire read and write channels (including the iterative decoder) as well as all the disk control and interface functions. There are currently two suppliers: Broadcom and Marvell.
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