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Physical verification is a process whereby an IC layout design is checked via EDA software tools to see if it meets certain criteria. Verification involves DRC (Design rule check), LVS (Layout versus schematic), ERC (Electrical Rule Check), XOR (Exclusive OR), and Antenna Checks.
This check is typically run after a metal spin, where the original and modified database are compared. This is done to confirm that the desired modifications have been made and no undesired modifications have been made by accident. This step involves comparing the two layout databases/GDS by XOR operation of the layout geometries. This check results a database which has all the mismatching geometries in both the layouts.
The antenna basically is a metal interconnect, i.e., a conductor like polysilicon or metal, that is not electrically connected to silicon or grounded, during the processing steps of the wafer. During the manufacturing process charge accumulation can occur on the antenna during certain fabrication steps like Plasma etching, which uses highly ionized matter to etch. If the connection to silicon does not exist, charges may build up on the interconnect to the point at which rapid discharge does take place and permanent physical damage results to thin transistor gate oxide. This rapid and destructive phenomenon is known as the antenna effect. Antenna errors can be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again.
The Antenna ratio is defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected.
ERC (Electrical rule check)
ERC (Electrical rule check) involves checking a design for all electrical connections those are considered dangerous. This might include checking for
- Well and substrate areas for proper contacts and spacings thereby ensuring correct power and ground connections
- Unconnected inputs or shorted outputs.
- Gates should not connect directly to supplies, it should be through TIE High/Low cells only.
ERC checks are based upon assumptions about the normal operating conditions of the ASIC, so they may give many false warning on ASICs with multiple or negative supplies. They can also check for structures susceptible to ESD damage
* Clein, Dan. (2000). CMOS IC Layout. Newnes. ISBN 0-7506-7194-7