A highly simplified illustration of the Zen microarchitecture: a core has a total of 512
KiB of L2 cache.
is the codename for a computer processor microarchitecture
, and was first used with their Ryzen
series of CPUs in February 2017. The first Zen-based preview system was demonstrated at E3 2016
, and first substantially detailed at an event hosted a block away from the Intel Developer Forum
2016. The first Zen-based CPUs codenamed "Summit Ridge" reached the market in early March 2017, Zen-derived Epyc
server processors launched in June 2017 and Zen-based APUs
arrived in November 2017.
Zen is a clean sheet design that differs from the long-standing Bulldozer architecture
. Zen-based processors use a 14 nm FinFET
process, are reportedly more energy efficient, and can execute significantly more instructions per cycle
has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache write-back
. Zen processors use three different sockets: desktop and mobile Ryzen chips use the AM4 socket
, bringing DDR4
support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 RAM and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket
; and Epyc server processors offer 128 PCI 3.0 lanes and octal-channel DDR4 using the SP3 socket
. Read more...