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For programmed I/O, the software that is running on the CPU uses instructions to perform data transfers to or from an I/O device. This is in contrast to Direct Memory Access (DMA) transfers. The term Programmed I/O can refer to either MMIO or PMIO. Port-mapped I/O (PMIO) refers to a special address space outside of normal memory that is accessed with instructions such as IN and OUT. Memory-mapped I/O (MMIO) refers to I/O devices being allocated addresses inside the normal Von Neumann address space that is primarily used for program and data. Such I/O is done using instructions such as LOAD and STORE. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices.
The best known example of a PC device that uses programmed I/O is the ATA interface; however, this interface can also be operated in any of several DMA modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, the PS/2 keyboard and mouse ports, legacy MIDI and joystick ports, the interval timer, and older network interfaces.
PIO mode in the ATA interface
Until the introduction of DMA, PIO was the only available method.
The PIO interface is grouped into different modes that correspond to different transfer rates. The electrical signaling among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.
The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually UDMA) interface was created to increase performance. The simple digital logic required to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are not required like in embedded systems, or with FPGA chips where PIO mode can be used without significant performance loss.
Two additional Advanced Timing modes have been defined in the CompactFlash specification 2.0. Those are PIO mode 5 and PIO mode 6. They are specific to CompactFlash.
|Mode||Maximum transfer rate (MB/s)||Minimum cycle time||Standard where spec is defined|
|Mode 0||3.3||600 ns||ATA-1|
|Mode 1||5.2||383 ns||ATA-1|
|Mode 2||8.3||240 ns||ATA-1|
|Mode 3||11.1||180 ns||ATA-2|
|Mode 4||16.7||120 ns||ATA-2|
|Mode 5||20||100 ns||CompactFlash 2.0|
|Mode 6||25||80 ns||CompactFlash 2.0|
PIO Mode 5
A PIO Mode 5 was proposed with operation at 22 MB/s, but was never implemented on hard disks because CPUs of the time would have been crippled waiting for the hard disk at the proposed PIO 5 timings, and the DMA standard ultimately obviated it. While no hard drives were ever manufactured to support this mode, some motherboard manufacturers preemptively provided BIOS support for it. PIO Mode 5 can be used with CompactFlash cards connected to IDE via CF-to-IDE adapters.
Not all devices are compatible with the official PIO timings. An example is the Sandisk SDDR-89 ImageMate 12-in-1 card reader which uses the GL819 chip from Genesys Logic, Inc. That chip has slightly different timings for most of its PIO Modes.
|GL819 timings||399 ns||249 ns||183 ns||133 ns||83 ns|
|ATA & CF spec timings||383 ns||240 ns||180 ns||120 ns||80 ns|
- WDMA - Single/Multiword DMA
- ATA - ATA specification
- List of device bandwidths