This article includes a list of references, related reading or external links, but its sources remain unclear because it lacks inline citations. (February 2014) (Learn how and when to remove this template message)
The R6000, not to be confused with the IBM RAD6000, is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS II instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.
The R6000 was implemented with emitter-coupled logic (ECL). In the mid- to late 1980s, the trend was to implement high-end microprocessors with high-speed logic such as ECL. As MIPS was a fabless company, the R6000 chip set was fabricated by Bipolar Integrated Technology.
The R6000 had few users. Control Data Systems (CDS) used an 80 MHz version in their high-end 4680-300 Series InforServer server. MIPS used the R6000 in their RC6260 and RC6280 servers.
- "MIPS Chip Set Implements Full ECL CPU". (December 1989). Microprocessor Report. pp. 1, 14–19.
- Horowitz, M. et al. (1990). "A 3.5ns, 1 Watt, ECL register file". ISSCC Digest of Technical Papers, pp. 68–59, 267.
- Roberts, D.; Layman, T.; Taylor, G. (1990). "An ECL RISC microprocessor designed for two level cache". Compcon Spring '90 Digest of Technical Papers, pp. 228–231.
- Thorson, M. (January 1990). "ECL Bus Controller Hits 266 Mbytes/s". Microprocessor Report. pp. 12–13.