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Oracle SPARC T5
|Produced||From 2013 to today|
|Max. CPU clock rate||3.6 GHz|
|Min. feature size||28 nm|
|Instruction set||SPARC V9|
|L1 cache||16×(16+16) KB|
|L2 cache||16×128 KB|
|L3 cache||8 MB|
SPARC T5 is the fifth generation multicore microprocessor of Oracle's SPARC T-Series family. It was first presented at Hot Chips 24 in August 2012, and was officially introduced with the Oracle SPARC T5 servers in March 2013. The processor is designed to offer high multithreaded performance (16 cores per chip, with 8 threads per core), as well as high single threaded performance from the same chip.
The processor uses the same SPARC S3 core design as its predecessor, the SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz. The S3 core is a dual-issue core that uses dynamic threading and out-of-order execution, incorporates one floating point unit, one dedicated cryptographic unit per core.
The 64-bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor, and scales up to 1,024 threads in an 8 socket system. Other changes include the support of PCIe version 3.0 and a new cache coherence protocol.
SPARC T5 and T4 compared
This chart shows some differences between the T5 and T4 processor chips.
|Processor||SPARC T5||SPARC T4|
|Max chips per system||8||4|
|Cores per chip||16||8|
|Max threads per chip||128||64|
|Frequency||3.6 GHz||2.85-3.0 GHz|
|Shared Level 3 cache||8 MB||4 MB|
|MCUs per chip||4||2|
|Transfer rate per MCU||12.8 Gbit/s||6.4 Gbit/s|
|Process Technology||28 nm||40 nm|
|Die size||478 mm2||403 mm2|
The SPARC T5 also introduces a new power management feature that consists of hardware support in the processor, and the software that allows system administrator to use the feature. Users select the policy how the system responds to over-temperature and over-current events. The dynamic voltage and frequency scaling (aka DVFS) policy can be set to maintain peak frequency, or to trade off between performance and power consumption.
SPARC T5 in systems
The T5 processor includes a crossbar network that connects the 16 cores with the L2 caches to the shared L3 cache. Multiprocessor cache coherence is maintained using a directory-based protocol. The design scales up to eight sockets without additional silicon (glueless). The snoopy based protocol used in SPARC T4 systems was replaced in order to reduce memory latency and reduce coherency bandwidth consumption.
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- Timothy Prickett Morgan (4 September 2012), "Oracle hurls Sparc T5 gladiators into big-iron arena", www.theregister.co.uk, The Register
- Timothy Prickett Morgan (26 March 2013), "Oracle's new T5 Sparcs boost scalability in chip and chassis", www.theregister.co.uk, The Register
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- John Feehrer; Sumti Jairath; Paul Loewenstein; Ram Sivaramakrishnan; David Smentek; Sebastian Turullols; Ali Vahidsafa (March–April 2013), IEEE Micro, vol. 33, no. 2, The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets, pp. 48-57, IEEE Computer Society, ISSN 0272-1732
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- "Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture, An Oracle White Paper, p. 29" (PDF), www.oracle.com, Oracle Corporation, February 2014
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- Jean Bozman (April 5, 2013), Oracle Launches T5 and M5 Servers: A New Generation of Oracle's SPARC/Solaris Servers, IDC, ISSN 0272-1732
- "SPARC T5 Deep Dive: An interview with Oracle's Rick Hetherington", www.oracle.com, Oracle Corporation