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SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on 27 September 2006 at the Fall 2006 Intel Developer Forum, with vague details in a white paper;[1] more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation.[2] SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4.[3]

SSE4 subsets[edit]

Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as SSE4.1 in some Intel documentation, is available in Penryn. Additionally, SSE4.2, a second subset consisting of the 7 remaining instructions, is first available in Nehalem-based Core i7. Intel credits feedback from developers as playing an important role in the development of the instruction set.

Starting with Barcelona-based processors, AMD introduced the SSE4a instruction set, which has 4 SSE4 instructions and 4 new SSE instructions. These instructions are not found in Intel's processors supporting SSE4.1 and AMD processors only started supporting Intel's SSE4.1 and SSE4.2 (the full SSE4 instruction set) in the Bulldozer-based FX processors. With SSE4a the misaligned SSE feature was also introduced which meant unaligned load instructions were as fast as aligned versions on aligned addresses. It also allowed disabling the alignment check on non-load SSE operations accessing memory.[4] Intel later introduced similar speed improvements to unaligned SSE in their Nehalem processors, but did not introduce misaligned access by non-load SSE instructions until AVX.[5]

Name confusion[edit]

What is now known as SSSE3 (Supplemental Streaming SIMD Extensions 3), introduced in the Intel Core 2 processor line, was referred to as SSE4 by some media until Intel came up with the SSSE3 moniker. Internally dubbed Merom New Instructions, Intel originally did not plan to assign a special name to them, which was criticized by some journalists.[6] Intel eventually cleared up the confusion and reserved the SSE4 name for their next instruction set extension.[7]

Intel is using the marketing term HD Boost to refer to SSE4.[8]

New instructions[edit]

Unlike all previous iterations of SSE, SSE4 contains instructions that execute operations which are not specific to multimedia applications. It features a number of instructions whose action is determined by a constant field and a set of instructions that take XMM0 as an implicit third operand.

Several of these instructions are enabled by the single-cycle shuffle engine in Penryn. (Shuffle operations reorder bytes within a register.)


These instructions were introduced with Penryn microarchitecture, the 45 nm shrink of Intel's Core microarchitecture. Support is indicated via the CPUID.01H:ECX.SSE41[Bit 19] flag.

Instruction Description
Compute eight offset sums of absolute differences, four at a time (i.e., |x0−y0|+|x1−y1|+|x2−y2|+|x3−y3|, |x0−y1|+|x1−y2|+|x2−y3|+|x3−y4|, …, |x0−y7|+|x1−y8|+|x2−y9|+|x3−y10|); this operation is important for some HD codecs, and allows an 8×8 block difference to be computed in fewer than seven cycles.[9] One bit of a three-bit immediate operand indicates whether y0 .. y10 or y4 .. y14 should be used from the destination operand, the other two whether x0..x3, x4..x7, x8..x11 or x12..x15 should be used from the source.
Sets the bottom unsigned 16-bit word of the destination to the smallest unsigned 16-bit word in the source, and the next-from-bottom to the index of that word in the source.
Packed signed multiplication on two sets of two out of four packed integers, the 1st and 3rd per packed 4, giving two packed 64-bit results.
Packed signed multiplication, four packed sets of 32-bit integers multiplied to give 4 packed 32-bit results.
Dot product for AOS (Array of Structs) data. This takes an immediate operand consisting of four (or two for DPPD) bits to select which of the entries in the input to multiply and accumulate, and another four (or two for DPPD) to select whether to put 0 or the dot-product in the appropriate field of the output.
Conditional copying of elements in one location with another, based (for non-V form) on the bits in an immediate operand, and (for V form) on the bits in register XMM0.
Packed minimum/maximum for different integer operand types
Round values in a floating-point register to integers, using one of four rounding modes specified by an immediate operand
The INSERTPS and PINSR instructions read 8, 16 or 32 bits from an x86 register or memory location and inserts it into a field in the destination register given by an immediate operand. EXTRACTPS and PEXTR read a field from the source register and insert it into an x86 register or memory location. For example, PEXTRD eax, [xmm0], 1; EXTRACTPS [addr+4*eax], xmm1, 1 stores the first field of xmm1 in the address given by the first field of xmm0.
Packed sign/zero extension to wider types
This is similar to the TEST instruction, in that it sets the Z flag to the result of an AND between its operands: ZF is set, if DEST AND SRC is equal to 0. Additionally it sets the C flag if (NOT DEST) AND SRC equals zero.

This is equivalent to setting the Z flag if none of the bits masked by SRC are set, and the C flag if all of the bits masked by SRC are set.

Quadword (64 bits) compare for equality
Convert signed DWORDs into unsigned WORDs with saturation.
Efficient read from write-combining memory area into SSE register; this is useful for retrieving results from peripherals attached to the memory bus.


SSE4.2 added STTNI (String and Text New Instructions),[10] several new instructions that perform character searches and comparison on two operands of 16 bytes at a time. These were designed (among other things) to speed up the parsing of XML documents.[11] It also added a CRC32 instruction to compute cyclic redundancy checks as used in certain data transfer protocols. These instructions were first implemented in the Nehalem-based Intel Core i7 product line and complete the SSE4 instruction set. Support is indicated via the CPUID.01H:ECX.SSE42[Bit 20] flag.

Instruction Description
Accumulate CRC32C value using the polynomial 0x11EDC6F41 (or, without the high order bit, 0x1EDC6F41).[12][13]
Packed Compare Explicit Length Strings, Return Index
Packed Compare Explicit Length Strings, Return Mask
Packed Compare Implicit Length Strings, Return Index
Packed Compare Implicit Length Strings, Return Mask
Compare Packed Signed 64-bit data For Greater Than

POPCNT and LZCNT[edit]

These instructions operate on integer rather than SSE registers, because they are not SIMD instructions, but appear at the same time and although introduced by AMD with the SSE4a instruction set, they are counted as separate extensions with their own dedicated CPUID bits to indicate support. Intel implements POPCNT beginning with the Nehalem microarchitecture and LZCNT beginning with the Haswell microarchitecture. AMD implements both beginning with the Barcelona microarchitecture.

AMD calls this pair of instructions Advanced Bit Manipulation (ABM).

Instruction Description
Population count (count number of bits set to 1). Support is indicated via the CPUID.01H:ECX.POPCNT[Bit 23] flag.[14]
Leading zero count. Support is indicated via the CPUID.80000001H:ECX.ABM[Bit 5] flag.[15]

The result of lzcnt is 31 minus the result of the bsr (bit scan reverse), except when the input is 0. lzcnt produces a result of 32, while bsr produces an undefined result (and sets the zero flag). The encoding of lzcnt is similar enough to bsr that if lzcnt is performed on a CPU not supporting it such as Intel CPU's prior to Haswell, it will perform the bsr operation instead of raising an invalid instruction error.

Trailing zeros can be counted using the existing bsf instruction.


The SSE4a instruction group was introduced in AMD's Barcelona microarchitecture. These instructions are not available in Intel processors. Support is indicated via the CPUID.80000001H:ECX.SSE4A[Bit 6] flag.[15]

Instruction Description
Combined mask-shift instructions.[16]
Scalar streaming store instructions.[17]

Supporting CPUs[edit]

  • Intel
    • Silvermont processors (SSE4.1, SSE4.2 and POPCNT supported)
    • Goldmont processors (SSE4.1, SSE4.2 and POPCNT supported)
    • Penryn processors (SSE4.1 supported)
    • Nehalem processors and newer (SSE4.1, SSE4.2 and POPCNT supported)
    • Haswell processors and newer (SSE4.1, SSE4.2, POPCNT and LZCNT supported)
  • AMD
    • Barcelona processors (SSE4a, POPCNT and LZCNT supported)
    • Bobcat processors (SSE4a, POPCNT and LZCNT supported)
    • Jaguar processors and newer (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
    • Puma processors and newer (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
    • Bulldozer processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
    • Piledriver processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)[18]
    • Steamroller processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
    • Excavator processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
    • Zen processors (SSE4a, SSE4.1, SSE4.2, POPCNT and LZCNT supported)
  • VIA
    • Nano processors (SSE4.1 supported)


External links[edit]