HP Saturn

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HP Saturn 1LT8 Clarke in HP 48SX

The Saturn family of 4-bit microprocessors was developed by Hewlett-Packard in the 1980s mainly for programmable scientific calculators / handheld computers,  and to some extent, printers and handheld logic analyzers. It succeeded the Nut family of processors used in earlier calculators. The original Saturn chip was first used in the HP-71B hand-held BASIC-programmable computer, introduced in 1984. Later models of the family powered the popular HP 48 series of calculators, among others. The HP 49 series initially used the Saturn CPU as well, until the NEC fab[nb 1] could no longer manufacture the processor for technical reasons in 2003. Therefore, starting with the HP 49g+ model in 2003, the calculators switched to a Samsung S3C2410 processor with an ARM920T core (part of the ARMv4T architecture) which ran an emulator of the Saturn hardware in software. In 2000, the HP 39G and HP 40G were the last calculators introduced based on the actual NEC fabricated Saturn hardware. The last calculators based on the Saturn emulator were the HP 39gs, HP 40gs and HP 50g in 2006, as well as the 2007 revision of the hp 48gII. The HP 50g, the last calculator utilizing this emulator, was discontinued in 2015 when Samsung stopped producing the ARM processor on which it was based.[1][2][3]


The Saturn architecture is a nibble serial design[4] as opposed to its Nut predecessor, which was bit-serial.[5] Internally, the Saturn CPU has four 4-bit data buses that allow for nearly 1-cycle per nibble performance with one or two buses acting as a source and one or two acting as a destination.[4] The smallest addressable word is a 4-bit nibble which can hold one binary-coded decimal (BCD) digit. Any unit of data in the registers larger than a nibble, whose start and end fall on nibble boundaries, and which can be up to 64-bits, can be operated on as a whole, but the Saturn CPU performs the operation serially internally on a nibble-by-nibble basis.[4]

The Saturn microprocessor is a hybrid 64-bit / 20-bit CPU hardware-wise but acts like a 4-bit processor in that it presents nibble-based data to programs and uses a nibble-based addressing system. The main registers (GPRs), along with the temporary registers, are fully 64-bits wide, but the address registers are only 20-bits wide. External logical data fetches are transparently converted to 8-bit physical fetches. The processor has a 20-bit address bus available to code but due to the fact that the processor addresses nibbles instead of bytes, only 19 bits are available externally.

The 1LT8 and later Saturn CPUs are equipped with four 64-bit GPRs (General Purpose Registers), named A, B, C and D. In addition, there are also five 64-bit "scratch" registers named R0, R1, R2, R3 and R4. These can only store data. If an ALU operation is required for data in a scratch register, then the register in question must be transferred to a GPR first. Other registers include a 1-nibble "pointer" register named P, usually used to select a nibble in a GPR or a range of nibbles (or for aligning immediate data on a specific nibble in a GPR, with wrap-around). For memory access, there are two 20-bit data pointer registers named D0 and D1. The Saturn CPU also has a PC or program counter register which can interoperate with the GPRs. There is also an 8-level, circular, LIFO 20-bit hardware return stack named RSTK used when a subroutine call instruction is issued. Additionally, the Saturn CPU is equipped with a 16-bit software status register named ST and a 1-nibble hardware status register named HS, which notably, contains the SB or "sticky bit" flag indicating whether a binary 1 was right shifted off of a GPR. Furthermore, the Saturn CPU has a 12-bit OUT register and a 16-bit IN register, which in the Yorke and Clarke SoCs, are used to capture input from the keyboard and also control the beeper. There is also a 1-bit carry flag register.

In addition to the above, the Saturn CPU has a simple, non-prioritized interrupt system. When an interrupt occurs, the CPU finishes executing the current instruction, saves the program counter to the hardware return stack (RSTK) and jumps to address 0x0000Fh hex, where the preceding value is in nibbles.[4] The CPU also interacts with the keyboard scanning logic directly.

The following diagram depicts the registers (with each white square being 4-bits / a nibble except for the Carry flag, which is 1 bit):

"Graphical representation of HP Saturn register fields"

Saturn 64-bit GPR register format and fields:

HP Saturn register fields
Bits 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11-8   7-4   3-0 
Nibble F E D C B A 9 8 7 6 5 4 3 2 1 0
Fields   XS B
P=0   P
P=7   WP

Data in the general purpose registers can be accessed via fields that fall on nibble boundaries, whereas the scratch registers allow only load and store operations. The fields, as shown in the above diagram, are W (whole 64-bit GPR), A (first 5 nibbles of a GPR), S (most significant nibble of a GPR), XS (nibble 2 of a GPR), M (nibbles 3-14 of a GPR), X (first 3 nibbles of a GPR) and B (first byte of a GPR). In addition, there is the P field which selects a nibble from a GPR based on the P register's 4-bit value. Also, there is the WP field which selects nibbles 0 through the nibble selected in the P register. The 64 bits (16 nibbles) can hold BCD-formatted coded floating point numbers composed of a sign nibble (which is "9" if the number is negative), 12 mantissa digits and a 3-digit 10's complement exponent stored in BCD format (±499).[6] The internal representation of BCD floating point values are a 15-digit mantissa with one sign nibble in one register combined with a 20-bit exponent, in 10's complement format, in another register. The use of BCD instead of straight binary representation is advantageous for calculators as it avoids rounding problems that occur on the binary/decimal conversion.

The Saturn CPU's addresses are also nibble-based. The three pointer registers (including the program counter) and address registers are 20 bits wide. Due to this, the Saturn architecture can address 1 M nibbles or, equivalently, 512 K bytes. Beyond that size (e.g. in the 48GX), bank switching is used.

In both the HP 48S/SX and 48G/GX series, the Saturn CPU core is integrated as part of a more complex integrated circuit (IC) SoC package, save for the original HP-71B handheld computer which used a separate chip for the Saturn processor. These packages have code names inspired by the members of the Lewis and Clark Expedition. The codename of the IC is Clarke in the S/SX, after William Clark, and Yorke in the G/GX, after Clark's manservant. The previous series of Saturn-based ICs were codenamed Lewis, after Meriwether Lewis.

Chipsets and applications[edit]

The original Saturn CPU gave its name to the entire instruction set architecture. Later chips had their own code names:

Level Processor codename Used in calculator models Properties
0 Saturn (1LF2) HP-44A, HP-71B (1984)
? (1LJ7) ThinkJet printers (1984), including one built into HP Integral PC (1985)
1 Saturn (1LK7) HP-18C (1986), HP-28C (1987), HP-71B 640 kHz, more instructions
Bert[7] (1LU7)[7] HP-10B (1988), HP-20S (1988), HP-21S 640 kHz, 10 KB ROM, 256 bytes RAM, LCD driver
Sacajawea[7] (1LR3, 1LE2) HP-14B, HP-22S, HP-32S (1988), HP-32S+, HP-32SII (1991) 640 kHz, 16 KB ROM, 512 bytes RAM, LCD driver
Lewis[7] (1LR2, 1LT8) HP-17B (1988), HP 17BII (1990), HP-19B (1988), HP 19BII (1990), HP-27S (1988), HP-28S (1988), HP-42S (1988) 1 MHz, 64 KB ROM, LCD driver, memory controller, IR control, 3V CMOS
2 Clarke[7] (1LT8)[7] HP 48SX (1990), HP 48S (1990) 2 MHz, LCD controller, memory controller, UART and IR control, more instructions
3 Yorke[7] 00048-80063[8] HP 38G (1995), HP 38G+ (1998), HP 39G (2000), HP 40G (2000), HP 48GX (1993), HP 48G (1993),[nb 1] HP 48G+ (1998), HP 49G (1999) 3.68-4 MHz, LCD controller, memory controller, UART and IR control, manufactured by NEC, more instructions, sometimes also known as Saturn 5 platform
New-Yorke HP 48GX prototype 8 MHz, LCD controller, memory controller, UART and IR control. This was only made as an internal HP prototype and never released in the wild.[citation needed][discuss]
4 Apple series (Big Apple,[7] Mid Apple,[7] Little Apple) hp 39g+ (2003), HP 39gs (2006), HP 40gs (2006), hp 49g+ (2003), hp 48gII (2003/2007), HP 50g (2006) Virtual version of the Yorke CPU emulated by members of the 48/75 MHz Samsung S3C2410 processor family with ARM920T core (of the ARMv4T architecture) aka Saturn+ with additional virtual instructions

The CPU codenames are inspired by members of the Lewis and Clark Expedition of 1804–1806, the first United States overland expedition to the Pacific coast and back.


  1. ^ a b In the HP 48G, the Saturn processor is labelled "NEC Japan, D3004GD, 00048-80063, 9738PX002".


  1. ^ Kuperus, Klaas (2015-03-04). "HP 50g: End of an era". forum.hp-prime.de. Moravia. Archived from the original on 2015-04-02.
  2. ^ Kuperus, Klaas (2015-03-06). "HP 50g not so good news?". HP Museum. Moravia. Archived from the original on 2018-07-08. Retrieved 2016-01-01.
  3. ^ Wessman, Timothy James (2015-12-26). "Windows 10 won't allow HP 50g USB drivers to be installed". HP Museum. Archived from the original on 2018-07-08. Retrieved 2016-01-01.
  4. ^ a b c d HP-71B Hardware Internal Design Specification Vol 1. Hewlett Packard Corporation. September 1984. p. 3-1.
  5. ^ HP-41C CPU, Display Driver, HP-IL, Data Storage, Timer IC, and Interface IC Specifications. Hewlett Packard Corporation. July 1981. p. 5.
  6. ^ Fernandes, Gilbert (2005-07-16) [1999-01-29]. "Chapter 56.1 Real number". In Rechlin, Eric (ed.). Introduction to Saturn Assembly Language. hpcalc.org (3rd ed.). p. 104. ID 1693. Archived from the original on 2018-11-13. Retrieved 2019-04-29. If the exponent is negative, the exponent is encoded as "1000 - ABS(exponent)" [1]
  7. ^ a b c d e f g h i Finseth, Craig A. (2016-12-23). "names". Archived from the original on 2017-12-21. Retrieved 2017-12-21.
  8. ^ Arnett, Dave (1994-05-03). "Name that chip!". Newsgroupcomp.sys.hp48. Archived from the original on 2019-04-29. Retrieved 2019-04-22.

Further reading[edit]

External links[edit]