In memory addressing for Intel x86 computer architectures, segment descriptors are a part of the segmentation unit, used for translating a logical address to a linear address. Segment descriptors describe the memory segment referred to in the logical address. The segment descriptor (8 bytes long in 80286 and later) contains the following fields:
- A segment base address
- The segment limit which specifies the segment size
- Access rights byte containing the protection mechanism information
- Control bits
The x86 and x86-64 segment descriptor has the following form:
|Base Address[31:24]||G||D/B||L||AVL||Segment Limit[19:16]||P||DPL||1||Type||C/E||R/W||A||Base Address[23:16]|
|Base Address[15:0]||Segment Limit[15:0]|
Where the fields stand for:
- Base Address
- 32 bit starting memory address of the segment
- Segment Limit
- 20 bit length of the segment. (More specifically, the address of the last accessible data, so the length is one more that the value stored here.) How exactly this should be interpreted depends on other bits of the segment descriptor.
- If clear, the limit is in units of bytes, with a maximum of 220 bytes. If set, the limit is in units of 4096-byte pages, for a maximum of 232 bytes.
- D=Default operand size
- If clear, this is a 16-bit code segment; if set, this is a 32-bit segment.
- If set, the maximum offset size for a data segment is increased to 32-bit 0xffffffff. Otherwise it's the 16-bit max 0x0000ffff. Essentially the same meaning as "D".
- If set, this is a 64-bit segment (and D must be zero), and code in this segment uses the 64-bit instruction encoding. "L" cannot be set at the same time as "D" aka "B".
- For software use, not used by hardware
- If clear, a "segment not present" exception is generated on any reference to this segment
- DPL=Descriptor privilege level
- Privilege level (ring) required to access this descriptor
- If set, this is a code segment descriptor. If clear, this is a data/stack segment descriptor, which has "D" replaced by "B", "C" replaced by "E"and "R" replaced by "W". This is in fact a special case of the 2-bit type field, where the preceding bit 12 cleared as "0" refers to more internal system descriptors, for LDT, LSS, and gates.
- Code in this segment may be called from less-privileged levels.
- If clear, the segment expands from base address up to base+limit. If set, it expands from maximum offset down to limit, a behavior usually used for stacks.
- If clear, the segment may be executed but not read from.
- If clear, the data segment may be read but not written to.
- This bit is set to 1 by hardware when the segment is accessed, and cleared by software.
- Bovet, D.P., & Cesati, M. (2000). Understanding the Linux Kernel (First Edition). O'Reilly & Associates, Inc.
- Tabak, Daniel (1995). Advanced Microprocessors. Mcgraw Hill Publishers. p. 149. ISBN 9780070628434.
- AMD64 Architecture Programmer's Manual Volume 2: System Programming (PDF) (Technical report). 2013. p. 80. Archived from the original (PDF) on 2018-02-18.
- Tabak, Daniel. Advanced Microprocessors. McGraw Hill and Co.
- Hall, Douglas. Microprocessors and Interfacing. McGraw Hill Publications.
- Robert R. Collins (August 1998). "The Segment Descriptor Cache". Dr Dobb's Journal.
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